Searched refs:IMX6QDL_CLK_IPU2_DI0_PRE_SEL (Results 1 – 3 of 3) sorted by relevance
49 #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 macro
60 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
604 …clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_… in imx6q_clocks_init()860 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); in imx6q_clocks_init()
