Searched refs:IMX5_CLK_PLL2_SW (Results 1 – 2 of 2) sorted by relevance
315 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx5_clocks_common_init()316 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx5_clocks_common_init()334 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx50_clocks_init()402 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx51_clocks_init()452 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()493 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx53_clocks_init()
125 #define IMX5_CLK_PLL2_SW 113 macro
