Searched refs:IMX5_CLK_IPU_DI0_GATE (Results 1 – 4 of 4) sorted by relevance
122 #define IMX5_CLK_IPU_DI0_GATE 110 macro
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
163 <&clks IMX5_CLK_IPU_DI0_GATE>,
261 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); in mx5_clocks_common_init()