Searched refs:I915_READ_FW (Results 1 – 12 of 12) sorted by relevance
177 I915_READ_FW(offset); in load_render_mocs()185 I915_READ_FW(offset); in load_render_mocs()375 if (wait_for_atomic((I915_READ_FW(reg) == 0), 50)) in handle_tlb_pending_event()491 vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); in switch_mmio()497 old_v = mmio->value = I915_READ_FW(mmio->reg); in switch_mmio()
213 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()217 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
151 (void)I915_READ_FW(reg); in intel_uncore_check_forcewake_domains()
326 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); in gmbus_wait()328 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); in gmbus_wait()407 val = I915_READ_FW(GMBUS3); in gmbus_xfer_read_chunk()
853 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()854 low = I915_READ_FW(low_frame); in i915_get_vblank_counter()855 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()911 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); in __intel_get_crtc_scanline_from_timestamp()917 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR); in __intel_get_crtc_scanline_from_timestamp()919 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); in __intel_get_crtc_scanline_from_timestamp()954 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()956 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()975 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()1043 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; in i915_get_crtc_scanoutpos()[all …]
1973 dsparb = I915_READ_FW(DSPARB); in vlv_atomic_update_fifo()1974 dsparb2 = I915_READ_FW(DSPARB2); in vlv_atomic_update_fifo()1990 dsparb = I915_READ_FW(DSPARB); in vlv_atomic_update_fifo()1991 dsparb2 = I915_READ_FW(DSPARB2); in vlv_atomic_update_fifo()2007 dsparb3 = I915_READ_FW(DSPARB3); in vlv_atomic_update_fifo()2008 dsparb2 = I915_READ_FW(DSPARB2); in vlv_atomic_update_fifo()9361 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; in gen6_check_mailbox_status()9384 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; in gen7_check_mailbox_status()9414 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { in sandybridge_pcode_read()9432 *val = I915_READ_FW(GEN6_PCODE_DATA); in sandybridge_pcode_read()[all …]
1715 I915_WRITE_FW(RING_HEAD(base), I915_READ_FW(RING_TAIL(base))); in gen3_stop_engine()1726 if (I915_READ_FW(RING_HEAD(base)) != 0) in gen3_stop_engine()1994 #define done (((reg_value = I915_READ_FW(reg)) & mask) == value) in __intel_wait_for_register_fw()
867 mcr = I915_READ_FW(GEN8_MCR_SELECTOR); in read_subslice_reg()876 ret = I915_READ_FW(reg); in read_subslice_reg()
1640 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); in capture_reg_state()1652 error->forcewake = I915_READ_FW(FORCEWAKE); in capture_reg_state()1659 error->forcewake = I915_READ_FW(FORCEWAKE_MT); in capture_reg_state()
1534 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); in gen6_drpc_info()2260 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; in i915_rps_boost_info()2261 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; in i915_rps_boost_info()2262 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; in i915_rps_boost_info()2263 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; in i915_rps_boost_info()
196 val = I915_READ_FW(RING_CTL(engine->mmio_base)); in engines_sample()
3629 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) macro3632 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
