Searched refs:HSW_PWR_WELL_CTL_REQ (Results 1 – 3 of 3) sorted by relevance
339 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); in hsw_power_well_requesters()409 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); in hsw_power_well_enable()438 val & ~HSW_PWR_WELL_CTL_REQ(id)); in hsw_power_well_disable()453 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); in icl_combo_phy_aux_power_well_enable()474 val & ~HSW_PWR_WELL_CTL_REQ(id)); in icl_combo_phy_aux_power_well_disable()488 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); in hsw_power_well_enabled()502 HSW_PWR_WELL_CTL_REQ(id), in assert_can_enable_dc9()727 u32 mask = HSW_PWR_WELL_CTL_REQ(id); in hsw_power_well_sync_hw()
8868 #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) macro
1290 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) in power_well_ctl_mmio_write()
