Searched refs:HSIO_PLL5G_CFG0_CORE_CLK_DIV (Results 1 – 2 of 2) sorted by relevance
458 ocelot_write(ocelot, HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | in ocelot_pll5_init()
32 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) macro
