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Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 3 of 3) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/meson/
Dmeson_vclk.c61 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
145 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
146 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
209 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
216 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
218 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
220 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
224 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
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/Linux-v4.19/drivers/clk/meson/
Daxg.h70 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
Dgxbb.h52 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro