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Searched refs:HHI_HDMI_PLL_CNTL (Results 1 – 3 of 3) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/meson/
Dmeson_vclk.c110 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro
251 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
257 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
268 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
270 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
275 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
431 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); in meson_hdmi_pll_set_params()
444 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
448 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
[all …]
/Linux-v4.19/drivers/clk/meson/
Dgxbb.c234 .reg_off = HHI_HDMI_PLL_CNTL,
239 .reg_off = HHI_HDMI_PLL_CNTL,
264 .reg_off = HHI_HDMI_PLL_CNTL,
269 .reg_off = HHI_HDMI_PLL_CNTL,
286 .reg_off = HHI_HDMI_PLL_CNTL,
291 .reg_off = HHI_HDMI_PLL_CNTL,
302 .reg_off = HHI_HDMI_PLL_CNTL + 4,
307 .reg_off = HHI_HDMI_PLL_CNTL + 8,
312 .reg_off = HHI_HDMI_PLL_CNTL + 8,
317 .reg_off = HHI_HDMI_PLL_CNTL + 8,
[all …]
Dgxbb.h97 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro