Searched refs:HDLC_ENCODING_DIFF_BIPHASE_LEVEL (Results 1 – 4 of 4) sorted by relevance
110 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 macro
4290 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4363 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4422 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: in sync_mode()
4727 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()4802 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()4979 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
4567 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ in hdlc_mode()