Searched refs:HALF_SLICE_CHICKEN2 (Results 1 – 5 of 5) sorted by relevance
119 {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
2790 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_broadwell_mmio_info()
281 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); in gen9_ctx_workarounds_init()
3082 return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) || in gen7_is_valid_mux_addr()3127 if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg) in mask_reg_value()
8691 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) macro
