Searched refs:GPLR (Results 1 – 9 of 9) sorted by relevance
220 !!(GPLR & BADGE4_GPIO_SDTYP1), in badge4_init()221 !!(GPLR & BADGE4_GPIO_SDTYP0)); in badge4_init()240 PGSR |= (GPLR & (BADGE4_GPIO_SDTYP0|BADGE4_GPIO_SDTYP1)); in badge4_init()
164 if (GPLR & SDA) in adv7171_send()176 unsigned gplr = GPLR; in adv7171_write()184 if (!(GPLR & SDA)) in adv7171_write()548 unsigned long phys = __PREG(GPLR) & PMD_MASK; in map_sa1100_gpio_regs()579 scr = GPLR; in get_assabet_scr()
59 gpio = GPLR; in sa11x0_pm_enter()
64 while ((GPLR & GPIO_GPIO10)) { in jornada_ssp_byte()
34 #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) macro362 if (GPLR(i) & GPIO_bit(i)) in pxa2xx_mfp_suspend()373 saved_gplr[i] = GPLR(i * 32); in pxa2xx_mfp_suspend()
53 GPLR = 0, /* pin level read-only */ enumerator111 void __iomem *gplr = gpio_reg(chip, offset, GPLR); in intel_gpio_get()
23 #define GPLR 0x004 /* pin level r/o */ macro101 void __iomem *gplr = gpio_reg(chip, offset, GPLR); in mrfld_gpio_get()
104 .membase = (void *)&GPLR,
1105 #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ macro
