Searched refs:GPCR (Results 1 – 14 of 14) sorted by relevance
182 GPCR = (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 | in badge4_init()197 GPCR = (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL); in badge4_init()201 GPCR = (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2); in badge4_init()205 GPCR = BADGE4_GPIO_MUXSEL0; in badge4_init()210 GPCR = BADGE4_GPIO_TESTPT_J7; in badge4_init()214 GPCR = BADGE4_GPIO_PCMEN5V; /* initially off */ in badge4_init()287 GPCR = BADGE4_GPIO_PCMEN5V; in badge4_set_5V()
131 GPCR = SDA; in adv7171_start()147 GPCR = SCK; in adv7171_send()152 GPCR = SDA; in adv7171_send()157 GPCR = SCK; in adv7171_send()167 GPCR = SCK | SDA; in adv7171_send()181 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ in adv7171_write()196 GPCR = (~gplr) & (SDA | SCK | MOD); in adv7171_write()488 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; in assabet_init()496 GPCR = GPIO_GPIO27; in assabet_init()
107 GPCR = ~gpio; in sa11x0_pm_enter()
133 GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */ in pleb_map_io()
135 GPCR = SHANNON_GPIO_CODEC_RESET; in shannon_map_io()
115 GPCR = GPIO_GPIO25; in jornada_ssp_start()
452 GPCR = GPIO_MBGNT; in sa1110_mb_disable()471 GPCR = GPIO_MBGNT; in sa1110_mb_enable()
262 GPCR = GPIO_GPIO20; /* stop gpio20 */ in jornada720_init()
331 GPCR = 0x0fffffff; /* All outputs are set low by default */ in h3xxx_map_io()
37 #define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) macro377 GPCR(i * 32) = ~PGSR(i); in pxa2xx_mfp_suspend()401 GPCR(i * 32) = ~saved_gplr[i]; in pxa2xx_mfp_resume()
56 GPCR, /* pin clear */ enumerator124 gpcr = gpio_reg(chip, offset, GPCR); in intel_gpio_set()
26 #define GPCR 0x04c /* pin clear w/o */ macro119 gpcr = gpio_reg(chip, offset, GPCR); in mrfld_gpio_set()
148 GPCR(2) = GPIO_bit(2);157 GPCR(3) = GPIO_bit(3);
1108 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ macro
