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Searched refs:GEN8_L3SQCREG4 (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_workarounds.c632 I915_WRITE(GEN8_L3SQCREG4, in gen9_gt_workarounds_apply()
633 I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES); in gen9_gt_workarounds_apply()
830 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in icl_gt_workarounds_apply()
857 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in icl_gt_workarounds_apply()
975 whitelist_reg(w, GEN8_L3SQCREG4); in skl_whitelist_build()
988 whitelist_reg(w, GEN8_L3SQCREG4); in kbl_whitelist_build()
Dintel_lrc.c1429 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1434 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1443 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
Di915_reg.h7448 #define GEN8_L3SQCREG4 _MMIO(0xb118) macro
/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dmmio_context.c117 {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
Dhandlers.c479 GEN8_L3SQCREG4,//_MMIO(0xb118)
2765 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_broadwell_mmio_info()