1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Embedded Trace Buffer driver
6 */
7
8 #include <asm/local.h>
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/err.h>
15 #include <linux/fs.h>
16 #include <linux/miscdevice.h>
17 #include <linux/uaccess.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/seq_file.h>
22 #include <linux/coresight.h>
23 #include <linux/amba/bus.h>
24 #include <linux/clk.h>
25 #include <linux/circ_buf.h>
26 #include <linux/mm.h>
27 #include <linux/perf_event.h>
28
29
30 #include "coresight-priv.h"
31
32 #define ETB_RAM_DEPTH_REG 0x004
33 #define ETB_STATUS_REG 0x00c
34 #define ETB_RAM_READ_DATA_REG 0x010
35 #define ETB_RAM_READ_POINTER 0x014
36 #define ETB_RAM_WRITE_POINTER 0x018
37 #define ETB_TRG 0x01c
38 #define ETB_CTL_REG 0x020
39 #define ETB_RWD_REG 0x024
40 #define ETB_FFSR 0x300
41 #define ETB_FFCR 0x304
42 #define ETB_ITMISCOP0 0xee0
43 #define ETB_ITTRFLINACK 0xee4
44 #define ETB_ITTRFLIN 0xee8
45 #define ETB_ITATBDATA0 0xeeC
46 #define ETB_ITATBCTR2 0xef0
47 #define ETB_ITATBCTR1 0xef4
48 #define ETB_ITATBCTR0 0xef8
49
50 /* register description */
51 /* STS - 0x00C */
52 #define ETB_STATUS_RAM_FULL BIT(0)
53 /* CTL - 0x020 */
54 #define ETB_CTL_CAPT_EN BIT(0)
55 /* FFCR - 0x304 */
56 #define ETB_FFCR_EN_FTC BIT(0)
57 #define ETB_FFCR_FON_MAN BIT(6)
58 #define ETB_FFCR_STOP_FI BIT(12)
59 #define ETB_FFCR_STOP_TRIGGER BIT(13)
60
61 #define ETB_FFCR_BIT 6
62 #define ETB_FFSR_BIT 1
63 #define ETB_FRAME_SIZE_WORDS 4
64
65 /**
66 * struct etb_drvdata - specifics associated to an ETB component
67 * @base: memory mapped base address for this component.
68 * @dev: the device entity associated to this component.
69 * @atclk: optional clock for the core parts of the ETB.
70 * @csdev: component vitals needed by the framework.
71 * @miscdev: specifics to handle "/dev/xyz.etb" entry.
72 * @spinlock: only one at a time pls.
73 * @reading: synchronise user space access to etb buffer.
74 * @mode: this ETB is being used.
75 * @buf: area of memory where ETB buffer content gets sent.
76 * @buffer_depth: size of @buf.
77 * @trigger_cntr: amount of words to store after a trigger.
78 */
79 struct etb_drvdata {
80 void __iomem *base;
81 struct device *dev;
82 struct clk *atclk;
83 struct coresight_device *csdev;
84 struct miscdevice miscdev;
85 spinlock_t spinlock;
86 local_t reading;
87 local_t mode;
88 u8 *buf;
89 u32 buffer_depth;
90 u32 trigger_cntr;
91 };
92
etb_get_buffer_depth(struct etb_drvdata * drvdata)93 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
94 {
95 u32 depth = 0;
96
97 pm_runtime_get_sync(drvdata->dev);
98
99 /* RO registers don't need locking */
100 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
101
102 pm_runtime_put(drvdata->dev);
103 return depth;
104 }
105
etb_enable_hw(struct etb_drvdata * drvdata)106 static void etb_enable_hw(struct etb_drvdata *drvdata)
107 {
108 int i;
109 u32 depth;
110
111 CS_UNLOCK(drvdata->base);
112
113 depth = drvdata->buffer_depth;
114 /* reset write RAM pointer address */
115 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
116 /* clear entire RAM buffer */
117 for (i = 0; i < depth; i++)
118 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
119
120 /* reset write RAM pointer address */
121 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
122 /* reset read RAM pointer address */
123 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
124
125 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
126 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
127 drvdata->base + ETB_FFCR);
128 /* ETB trace capture enable */
129 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
130
131 CS_LOCK(drvdata->base);
132 }
133
etb_enable(struct coresight_device * csdev,u32 mode)134 static int etb_enable(struct coresight_device *csdev, u32 mode)
135 {
136 u32 val;
137 unsigned long flags;
138 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
139
140 val = local_cmpxchg(&drvdata->mode,
141 CS_MODE_DISABLED, mode);
142 /*
143 * When accessing from Perf, a HW buffer can be handled
144 * by a single trace entity. In sysFS mode many tracers
145 * can be logging to the same HW buffer.
146 */
147 if (val == CS_MODE_PERF)
148 return -EBUSY;
149
150 /* Nothing to do, the tracer is already enabled. */
151 if (val == CS_MODE_SYSFS)
152 goto out;
153
154 spin_lock_irqsave(&drvdata->spinlock, flags);
155 etb_enable_hw(drvdata);
156 spin_unlock_irqrestore(&drvdata->spinlock, flags);
157
158 out:
159 dev_info(drvdata->dev, "ETB enabled\n");
160 return 0;
161 }
162
etb_disable_hw(struct etb_drvdata * drvdata)163 static void etb_disable_hw(struct etb_drvdata *drvdata)
164 {
165 u32 ffcr;
166
167 CS_UNLOCK(drvdata->base);
168
169 ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
170 /* stop formatter when a stop has completed */
171 ffcr |= ETB_FFCR_STOP_FI;
172 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
173 /* manually generate a flush of the system */
174 ffcr |= ETB_FFCR_FON_MAN;
175 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
176
177 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
178 dev_err(drvdata->dev,
179 "timeout while waiting for completion of Manual Flush\n");
180 }
181
182 /* disable trace capture */
183 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
184
185 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
186 dev_err(drvdata->dev,
187 "timeout while waiting for Formatter to Stop\n");
188 }
189
190 CS_LOCK(drvdata->base);
191 }
192
etb_dump_hw(struct etb_drvdata * drvdata)193 static void etb_dump_hw(struct etb_drvdata *drvdata)
194 {
195 bool lost = false;
196 int i;
197 u8 *buf_ptr;
198 u32 read_data, depth;
199 u32 read_ptr, write_ptr;
200 u32 frame_off, frame_endoff;
201
202 CS_UNLOCK(drvdata->base);
203
204 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
205 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
206
207 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
208 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
209 if (frame_off) {
210 dev_err(drvdata->dev,
211 "write_ptr: %lu not aligned to formatter frame size\n",
212 (unsigned long)write_ptr);
213 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
214 (unsigned long)frame_off, (unsigned long)frame_endoff);
215 write_ptr += frame_endoff;
216 }
217
218 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
219 & ETB_STATUS_RAM_FULL) == 0) {
220 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
221 } else {
222 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
223 lost = true;
224 }
225
226 depth = drvdata->buffer_depth;
227 buf_ptr = drvdata->buf;
228 for (i = 0; i < depth; i++) {
229 read_data = readl_relaxed(drvdata->base +
230 ETB_RAM_READ_DATA_REG);
231 *(u32 *)buf_ptr = read_data;
232 buf_ptr += 4;
233 }
234
235 if (lost)
236 coresight_insert_barrier_packet(drvdata->buf);
237
238 if (frame_off) {
239 buf_ptr -= (frame_endoff * 4);
240 for (i = 0; i < frame_endoff; i++) {
241 *buf_ptr++ = 0x0;
242 *buf_ptr++ = 0x0;
243 *buf_ptr++ = 0x0;
244 *buf_ptr++ = 0x0;
245 }
246 }
247
248 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
249
250 CS_LOCK(drvdata->base);
251 }
252
etb_disable(struct coresight_device * csdev)253 static void etb_disable(struct coresight_device *csdev)
254 {
255 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
256 unsigned long flags;
257
258 spin_lock_irqsave(&drvdata->spinlock, flags);
259 etb_disable_hw(drvdata);
260 etb_dump_hw(drvdata);
261 spin_unlock_irqrestore(&drvdata->spinlock, flags);
262
263 local_set(&drvdata->mode, CS_MODE_DISABLED);
264
265 dev_info(drvdata->dev, "ETB disabled\n");
266 }
267
etb_alloc_buffer(struct coresight_device * csdev,int cpu,void ** pages,int nr_pages,bool overwrite)268 static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
269 void **pages, int nr_pages, bool overwrite)
270 {
271 int node;
272 struct cs_buffers *buf;
273
274 if (cpu == -1)
275 cpu = smp_processor_id();
276 node = cpu_to_node(cpu);
277
278 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
279 if (!buf)
280 return NULL;
281
282 buf->snapshot = overwrite;
283 buf->nr_pages = nr_pages;
284 buf->data_pages = pages;
285
286 return buf;
287 }
288
etb_free_buffer(void * config)289 static void etb_free_buffer(void *config)
290 {
291 struct cs_buffers *buf = config;
292
293 kfree(buf);
294 }
295
etb_set_buffer(struct coresight_device * csdev,struct perf_output_handle * handle,void * sink_config)296 static int etb_set_buffer(struct coresight_device *csdev,
297 struct perf_output_handle *handle,
298 void *sink_config)
299 {
300 int ret = 0;
301 unsigned long head;
302 struct cs_buffers *buf = sink_config;
303
304 /* wrap head around to the amount of space we have */
305 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
306
307 /* find the page to write to */
308 buf->cur = head / PAGE_SIZE;
309
310 /* and offset within that page */
311 buf->offset = head % PAGE_SIZE;
312
313 local_set(&buf->data_size, 0);
314
315 return ret;
316 }
317
etb_reset_buffer(struct coresight_device * csdev,struct perf_output_handle * handle,void * sink_config)318 static unsigned long etb_reset_buffer(struct coresight_device *csdev,
319 struct perf_output_handle *handle,
320 void *sink_config)
321 {
322 unsigned long size = 0;
323 struct cs_buffers *buf = sink_config;
324
325 if (buf) {
326 /*
327 * In snapshot mode ->data_size holds the new address of the
328 * ring buffer's head. The size itself is the whole address
329 * range since we want the latest information.
330 */
331 if (buf->snapshot)
332 handle->head = local_xchg(&buf->data_size,
333 buf->nr_pages << PAGE_SHIFT);
334
335 /*
336 * Tell the tracer PMU how much we got in this run and if
337 * something went wrong along the way. Nobody else can use
338 * this cs_buffers instance until we are done. As such
339 * resetting parameters here and squaring off with the ring
340 * buffer API in the tracer PMU is fine.
341 */
342 size = local_xchg(&buf->data_size, 0);
343 }
344
345 return size;
346 }
347
etb_update_buffer(struct coresight_device * csdev,struct perf_output_handle * handle,void * sink_config)348 static void etb_update_buffer(struct coresight_device *csdev,
349 struct perf_output_handle *handle,
350 void *sink_config)
351 {
352 bool lost = false;
353 int i, cur;
354 u8 *buf_ptr;
355 const u32 *barrier;
356 u32 read_ptr, write_ptr, capacity;
357 u32 status, read_data, to_read;
358 unsigned long offset;
359 struct cs_buffers *buf = sink_config;
360 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
361
362 if (!buf)
363 return;
364
365 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
366
367 etb_disable_hw(drvdata);
368 CS_UNLOCK(drvdata->base);
369
370 /* unit is in words, not bytes */
371 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
372 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
373
374 /*
375 * Entries should be aligned to the frame size. If they are not
376 * go back to the last alignment point to give decoding tools a
377 * chance to fix things.
378 */
379 if (write_ptr % ETB_FRAME_SIZE_WORDS) {
380 dev_err(drvdata->dev,
381 "write_ptr: %lu not aligned to formatter frame size\n",
382 (unsigned long)write_ptr);
383
384 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
385 lost = true;
386 }
387
388 /*
389 * Get a hold of the status register and see if a wrap around
390 * has occurred. If so adjust things accordingly. Otherwise
391 * start at the beginning and go until the write pointer has
392 * been reached.
393 */
394 status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
395 if (status & ETB_STATUS_RAM_FULL) {
396 lost = true;
397 to_read = capacity;
398 read_ptr = write_ptr;
399 } else {
400 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth);
401 to_read *= ETB_FRAME_SIZE_WORDS;
402 }
403
404 /*
405 * Make sure we don't overwrite data that hasn't been consumed yet.
406 * It is entirely possible that the HW buffer has more data than the
407 * ring buffer can currently handle. If so adjust the start address
408 * to take only the last traces.
409 *
410 * In snapshot mode we are looking to get the latest traces only and as
411 * such, we don't care about not overwriting data that hasn't been
412 * processed by user space.
413 */
414 if (!buf->snapshot && to_read > handle->size) {
415 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1);
416
417 /* The new read pointer must be frame size aligned */
418 to_read = handle->size & mask;
419 /*
420 * Move the RAM read pointer up, keeping in mind that
421 * everything is in frame size units.
422 */
423 read_ptr = (write_ptr + drvdata->buffer_depth) -
424 to_read / ETB_FRAME_SIZE_WORDS;
425 /* Wrap around if need be*/
426 if (read_ptr > (drvdata->buffer_depth - 1))
427 read_ptr -= drvdata->buffer_depth;
428 /* let the decoder know we've skipped ahead */
429 lost = true;
430 }
431
432 if (lost)
433 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
434
435 /* finally tell HW where we want to start reading from */
436 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
437
438 cur = buf->cur;
439 offset = buf->offset;
440 barrier = barrier_pkt;
441
442 for (i = 0; i < to_read; i += 4) {
443 buf_ptr = buf->data_pages[cur] + offset;
444 read_data = readl_relaxed(drvdata->base +
445 ETB_RAM_READ_DATA_REG);
446 if (lost && i < CORESIGHT_BARRIER_PKT_SIZE) {
447 read_data = *barrier;
448 barrier++;
449 }
450
451 *(u32 *)buf_ptr = read_data;
452 buf_ptr += 4;
453
454 offset += 4;
455 if (offset >= PAGE_SIZE) {
456 offset = 0;
457 cur++;
458 /* wrap around at the end of the buffer */
459 cur &= buf->nr_pages - 1;
460 }
461 }
462
463 /* reset ETB buffer for next run */
464 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
465 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
466
467 /*
468 * In snapshot mode all we have to do is communicate to
469 * perf_aux_output_end() the address of the current head. In full
470 * trace mode the same function expects a size to move rb->aux_head
471 * forward.
472 */
473 if (buf->snapshot)
474 local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
475 else
476 local_add(to_read, &buf->data_size);
477
478 etb_enable_hw(drvdata);
479 CS_LOCK(drvdata->base);
480 }
481
482 static const struct coresight_ops_sink etb_sink_ops = {
483 .enable = etb_enable,
484 .disable = etb_disable,
485 .alloc_buffer = etb_alloc_buffer,
486 .free_buffer = etb_free_buffer,
487 .set_buffer = etb_set_buffer,
488 .reset_buffer = etb_reset_buffer,
489 .update_buffer = etb_update_buffer,
490 };
491
492 static const struct coresight_ops etb_cs_ops = {
493 .sink_ops = &etb_sink_ops,
494 };
495
etb_dump(struct etb_drvdata * drvdata)496 static void etb_dump(struct etb_drvdata *drvdata)
497 {
498 unsigned long flags;
499
500 spin_lock_irqsave(&drvdata->spinlock, flags);
501 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
502 etb_disable_hw(drvdata);
503 etb_dump_hw(drvdata);
504 etb_enable_hw(drvdata);
505 }
506 spin_unlock_irqrestore(&drvdata->spinlock, flags);
507
508 dev_info(drvdata->dev, "ETB dumped\n");
509 }
510
etb_open(struct inode * inode,struct file * file)511 static int etb_open(struct inode *inode, struct file *file)
512 {
513 struct etb_drvdata *drvdata = container_of(file->private_data,
514 struct etb_drvdata, miscdev);
515
516 if (local_cmpxchg(&drvdata->reading, 0, 1))
517 return -EBUSY;
518
519 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
520 return 0;
521 }
522
etb_read(struct file * file,char __user * data,size_t len,loff_t * ppos)523 static ssize_t etb_read(struct file *file, char __user *data,
524 size_t len, loff_t *ppos)
525 {
526 u32 depth;
527 struct etb_drvdata *drvdata = container_of(file->private_data,
528 struct etb_drvdata, miscdev);
529
530 etb_dump(drvdata);
531
532 depth = drvdata->buffer_depth;
533 if (*ppos + len > depth * 4)
534 len = depth * 4 - *ppos;
535
536 if (copy_to_user(data, drvdata->buf + *ppos, len)) {
537 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
538 return -EFAULT;
539 }
540
541 *ppos += len;
542
543 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
544 __func__, len, (int)(depth * 4 - *ppos));
545 return len;
546 }
547
etb_release(struct inode * inode,struct file * file)548 static int etb_release(struct inode *inode, struct file *file)
549 {
550 struct etb_drvdata *drvdata = container_of(file->private_data,
551 struct etb_drvdata, miscdev);
552 local_set(&drvdata->reading, 0);
553
554 dev_dbg(drvdata->dev, "%s: released\n", __func__);
555 return 0;
556 }
557
558 static const struct file_operations etb_fops = {
559 .owner = THIS_MODULE,
560 .open = etb_open,
561 .read = etb_read,
562 .release = etb_release,
563 .llseek = no_llseek,
564 };
565
566 #define coresight_etb10_reg(name, offset) \
567 coresight_simple_reg32(struct etb_drvdata, name, offset)
568
569 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG);
570 coresight_etb10_reg(sts, ETB_STATUS_REG);
571 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER);
572 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER);
573 coresight_etb10_reg(trg, ETB_TRG);
574 coresight_etb10_reg(ctl, ETB_CTL_REG);
575 coresight_etb10_reg(ffsr, ETB_FFSR);
576 coresight_etb10_reg(ffcr, ETB_FFCR);
577
578 static struct attribute *coresight_etb_mgmt_attrs[] = {
579 &dev_attr_rdp.attr,
580 &dev_attr_sts.attr,
581 &dev_attr_rrp.attr,
582 &dev_attr_rwp.attr,
583 &dev_attr_trg.attr,
584 &dev_attr_ctl.attr,
585 &dev_attr_ffsr.attr,
586 &dev_attr_ffcr.attr,
587 NULL,
588 };
589
trigger_cntr_show(struct device * dev,struct device_attribute * attr,char * buf)590 static ssize_t trigger_cntr_show(struct device *dev,
591 struct device_attribute *attr, char *buf)
592 {
593 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
594 unsigned long val = drvdata->trigger_cntr;
595
596 return sprintf(buf, "%#lx\n", val);
597 }
598
trigger_cntr_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)599 static ssize_t trigger_cntr_store(struct device *dev,
600 struct device_attribute *attr,
601 const char *buf, size_t size)
602 {
603 int ret;
604 unsigned long val;
605 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
606
607 ret = kstrtoul(buf, 16, &val);
608 if (ret)
609 return ret;
610
611 drvdata->trigger_cntr = val;
612 return size;
613 }
614 static DEVICE_ATTR_RW(trigger_cntr);
615
616 static struct attribute *coresight_etb_attrs[] = {
617 &dev_attr_trigger_cntr.attr,
618 NULL,
619 };
620
621 static const struct attribute_group coresight_etb_group = {
622 .attrs = coresight_etb_attrs,
623 };
624
625 static const struct attribute_group coresight_etb_mgmt_group = {
626 .attrs = coresight_etb_mgmt_attrs,
627 .name = "mgmt",
628 };
629
630 const struct attribute_group *coresight_etb_groups[] = {
631 &coresight_etb_group,
632 &coresight_etb_mgmt_group,
633 NULL,
634 };
635
etb_probe(struct amba_device * adev,const struct amba_id * id)636 static int etb_probe(struct amba_device *adev, const struct amba_id *id)
637 {
638 int ret;
639 void __iomem *base;
640 struct device *dev = &adev->dev;
641 struct coresight_platform_data *pdata = NULL;
642 struct etb_drvdata *drvdata;
643 struct resource *res = &adev->res;
644 struct coresight_desc desc = { 0 };
645 struct device_node *np = adev->dev.of_node;
646
647 if (np) {
648 pdata = of_get_coresight_platform_data(dev, np);
649 if (IS_ERR(pdata))
650 return PTR_ERR(pdata);
651 adev->dev.platform_data = pdata;
652 }
653
654 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
655 if (!drvdata)
656 return -ENOMEM;
657
658 drvdata->dev = &adev->dev;
659 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
660 if (!IS_ERR(drvdata->atclk)) {
661 ret = clk_prepare_enable(drvdata->atclk);
662 if (ret)
663 return ret;
664 }
665 dev_set_drvdata(dev, drvdata);
666
667 /* validity for the resource is already checked by the AMBA core */
668 base = devm_ioremap_resource(dev, res);
669 if (IS_ERR(base))
670 return PTR_ERR(base);
671
672 drvdata->base = base;
673
674 spin_lock_init(&drvdata->spinlock);
675
676 drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
677 pm_runtime_put(&adev->dev);
678
679 if (drvdata->buffer_depth & 0x80000000)
680 return -EINVAL;
681
682 drvdata->buf = devm_kcalloc(dev,
683 drvdata->buffer_depth, 4, GFP_KERNEL);
684 if (!drvdata->buf)
685 return -ENOMEM;
686
687 desc.type = CORESIGHT_DEV_TYPE_SINK;
688 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
689 desc.ops = &etb_cs_ops;
690 desc.pdata = pdata;
691 desc.dev = dev;
692 desc.groups = coresight_etb_groups;
693 drvdata->csdev = coresight_register(&desc);
694 if (IS_ERR(drvdata->csdev))
695 return PTR_ERR(drvdata->csdev);
696
697 drvdata->miscdev.name = pdata->name;
698 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
699 drvdata->miscdev.fops = &etb_fops;
700 ret = misc_register(&drvdata->miscdev);
701 if (ret)
702 goto err_misc_register;
703
704 return 0;
705
706 err_misc_register:
707 coresight_unregister(drvdata->csdev);
708 return ret;
709 }
710
711 #ifdef CONFIG_PM
etb_runtime_suspend(struct device * dev)712 static int etb_runtime_suspend(struct device *dev)
713 {
714 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
715
716 if (drvdata && !IS_ERR(drvdata->atclk))
717 clk_disable_unprepare(drvdata->atclk);
718
719 return 0;
720 }
721
etb_runtime_resume(struct device * dev)722 static int etb_runtime_resume(struct device *dev)
723 {
724 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
725
726 if (drvdata && !IS_ERR(drvdata->atclk))
727 clk_prepare_enable(drvdata->atclk);
728
729 return 0;
730 }
731 #endif
732
733 static const struct dev_pm_ops etb_dev_pm_ops = {
734 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
735 };
736
737 static const struct amba_id etb_ids[] = {
738 {
739 .id = 0x000bb907,
740 .mask = 0x000fffff,
741 },
742 { 0, 0},
743 };
744
745 static struct amba_driver etb_driver = {
746 .drv = {
747 .name = "coresight-etb10",
748 .owner = THIS_MODULE,
749 .pm = &etb_dev_pm_ops,
750 .suppress_bind_attrs = true,
751
752 },
753 .probe = etb_probe,
754 .id_table = etb_ids,
755 };
756 builtin_amba_driver(etb_driver);
757
