Searched refs:ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 9 of 9) sorted by relevance
108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
1294 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()1373 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
4304 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()4390 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
5452 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()5569 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
377 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
832 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
