Searched refs:EN0 (Results 1 – 6 of 6) sorted by relevance
21 simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1); in simpad_pcmcia_hw_init()66 simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1); in simpad_pcmcia_configure_socket()71 simpad_set_cs3_bit(VCC_5V_EN|EN0); in simpad_pcmcia_configure_socket()76 simpad_set_cs3_bit(VCC_3V_EN|EN0); in simpad_pcmcia_configure_socket()82 simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1); in simpad_pcmcia_configure_socket()
171 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()173 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()175 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()177 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()179 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()181 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()183 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()185 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()187 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()189 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()[all …]
22 #define EN0 0x04 macro
34 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.73 hardware input to PMIC i.e. EN0, EN1 or79 for hardware input pin EN0.
101 #define EN0 0x0008 /* Both should be enable for 3.3V or 5V */ macro
207 cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | in simpad_map_io()
