1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL92D_REG_H__ 27 #define __RTL92D_REG_H__ 28 29 /* ----------------------------------------------------- */ 30 /* 0x0000h ~ 0x00FFh System Configuration */ 31 /* ----------------------------------------------------- */ 32 #define REG_SYS_ISO_CTRL 0x0000 33 #define REG_SYS_FUNC_EN 0x0002 34 #define REG_APS_FSMCO 0x0004 35 #define REG_SYS_CLKR 0x0008 36 #define REG_9346CR 0x000A 37 #define REG_EE_VPD 0x000C 38 #define REG_AFE_MISC 0x0010 39 #define REG_SPS0_CTRL 0x0011 40 #define REG_POWER_OFF_IN_PROCESS 0x0017 41 #define REG_SPS_OCP_CFG 0x0018 42 #define REG_RSV_CTRL 0x001C 43 #define REG_RF_CTRL 0x001F 44 #define REG_LDOA15_CTRL 0x0020 45 #define REG_LDOV12D_CTRL 0x0021 46 #define REG_LDOHCI12_CTRL 0x0022 47 #define REG_LPLDO_CTRL 0x0023 48 #define REG_AFE_XTAL_CTRL 0x0024 49 #define REG_AFE_PLL_CTRL 0x0028 50 /* for 92d, DMDP,SMSP,DMSP contrl */ 51 #define REG_MAC_PHY_CTRL 0x002c 52 #define REG_EFUSE_CTRL 0x0030 53 #define REG_EFUSE_TEST 0x0034 54 #define REG_PWR_DATA 0x0038 55 #define REG_CAL_TIMER 0x003C 56 #define REG_ACLK_MON 0x003E 57 #define REG_GPIO_MUXCFG 0x0040 58 #define REG_GPIO_IO_SEL 0x0042 59 #define REG_MAC_PINMUX_CFG 0x0043 60 #define REG_GPIO_PIN_CTRL 0x0044 61 #define REG_GPIO_INTM 0x0048 62 #define REG_LEDCFG0 0x004C 63 #define REG_LEDCFG1 0x004D 64 #define REG_LEDCFG2 0x004E 65 #define REG_LEDCFG3 0x004F 66 #define REG_FSIMR 0x0050 67 #define REG_FSISR 0x0054 68 69 #define REG_MCUFWDL 0x0080 70 71 #define REG_HMEBOX_EXT_0 0x0088 72 #define REG_HMEBOX_EXT_1 0x008A 73 #define REG_HMEBOX_EXT_2 0x008C 74 #define REG_HMEBOX_EXT_3 0x008E 75 76 #define REG_BIST_SCAN 0x00D0 77 #define REG_BIST_RPT 0x00D4 78 #define REG_BIST_ROM_RPT 0x00D8 79 #define REG_USB_SIE_INTF 0x00E0 80 #define REG_PCIE_MIO_INTF 0x00E4 81 #define REG_PCIE_MIO_INTD 0x00E8 82 #define REG_HPON_FSM 0x00EC 83 #define REG_SYS_CFG 0x00F0 84 #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 85 86 #define REG_MAC0 0x0081 87 #define REG_MAC1 0x0053 88 #define FW_MAC0_READY 0x18 89 #define FW_MAC1_READY 0x1A 90 #define MAC0_ON BIT(7) 91 #define MAC1_ON BIT(0) 92 #define MAC0_READY BIT(0) 93 #define MAC1_READY BIT(0) 94 95 /* ----------------------------------------------------- */ 96 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 97 /* ----------------------------------------------------- */ 98 #define REG_CR 0x0100 99 #define REG_PBP 0x0104 100 #define REG_TRXDMA_CTRL 0x010C 101 #define REG_TRXFF_BNDY 0x0114 102 #define REG_TRXFF_STATUS 0x0118 103 #define REG_RXFF_PTR 0x011C 104 #define REG_HIMR 0x0120 105 #define REG_HISR 0x0124 106 #define REG_HIMRE 0x0128 107 #define REG_HISRE 0x012C 108 #define REG_CPWM 0x012F 109 #define REG_FWIMR 0x0130 110 #define REG_FWISR 0x0134 111 #define REG_PKTBUF_DBG_CTRL 0x0140 112 #define REG_PKTBUF_DBG_DATA_L 0x0144 113 #define REG_PKTBUF_DBG_DATA_H 0x0148 114 115 #define REG_TC0_CTRL 0x0150 116 #define REG_TC1_CTRL 0x0154 117 #define REG_TC2_CTRL 0x0158 118 #define REG_TC3_CTRL 0x015C 119 #define REG_TC4_CTRL 0x0160 120 #define REG_TCUNIT_BASE 0x0164 121 #define REG_MBIST_START 0x0174 122 #define REG_MBIST_DONE 0x0178 123 #define REG_MBIST_FAIL 0x017C 124 #define REG_C2HEVT_MSG_NORMAL 0x01A0 125 #define REG_C2HEVT_MSG_TEST 0x01B8 126 #define REG_C2HEVT_CLEAR 0x01BF 127 #define REG_MCUTST_1 0x01c0 128 #define REG_FMETHR 0x01C8 129 #define REG_HMETFR 0x01CC 130 #define REG_HMEBOX_0 0x01D0 131 #define REG_HMEBOX_1 0x01D4 132 #define REG_HMEBOX_2 0x01D8 133 #define REG_HMEBOX_3 0x01DC 134 135 #define REG_LLT_INIT 0x01E0 136 #define REG_BB_ACCEESS_CTRL 0x01E8 137 #define REG_BB_ACCESS_DATA 0x01EC 138 139 140 /* ----------------------------------------------------- */ 141 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 142 /* ----------------------------------------------------- */ 143 #define REG_RQPN 0x0200 144 #define REG_FIFOPAGE 0x0204 145 #define REG_TDECTRL 0x0208 146 #define REG_TXDMA_OFFSET_CHK 0x020C 147 #define REG_TXDMA_STATUS 0x0210 148 #define REG_RQPN_NPQ 0x0214 149 150 /* ----------------------------------------------------- */ 151 /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 152 /* ----------------------------------------------------- */ 153 #define REG_RXDMA_AGG_PG_TH 0x0280 154 #define REG_RXPKT_NUM 0x0284 155 #define REG_RXDMA_STATUS 0x0288 156 157 /* ----------------------------------------------------- */ 158 /* 0x0300h ~ 0x03FFh PCIe */ 159 /* ----------------------------------------------------- */ 160 #define REG_PCIE_CTRL_REG 0x0300 161 #define REG_INT_MIG 0x0304 162 #define REG_BCNQ_DESA 0x0308 163 #define REG_HQ_DESA 0x0310 164 #define REG_MGQ_DESA 0x0318 165 #define REG_VOQ_DESA 0x0320 166 #define REG_VIQ_DESA 0x0328 167 #define REG_BEQ_DESA 0x0330 168 #define REG_BKQ_DESA 0x0338 169 #define REG_RX_DESA 0x0340 170 #define REG_DBI 0x0348 171 #define REG_DBI_WDATA 0x0348 172 #define REG_DBI_RDATA 0x034C 173 #define REG_DBI_CTRL 0x0350 174 #define REG_DBI_FLAG 0x0352 175 #define REG_MDIO 0x0354 176 #define REG_DBG_SEL 0x0360 177 #define REG_PCIE_HRPWM 0x0361 178 #define REG_PCIE_HCPWM 0x0363 179 #define REG_UART_CTRL 0x0364 180 #define REG_UART_TX_DESA 0x0370 181 #define REG_UART_RX_DESA 0x0378 182 183 /* ----------------------------------------------------- */ 184 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 185 /* ----------------------------------------------------- */ 186 #define REG_VOQ_INFORMATION 0x0400 187 #define REG_VIQ_INFORMATION 0x0404 188 #define REG_BEQ_INFORMATION 0x0408 189 #define REG_BKQ_INFORMATION 0x040C 190 #define REG_MGQ_INFORMATION 0x0410 191 #define REG_HGQ_INFORMATION 0x0414 192 #define REG_BCNQ_INFORMATION 0x0418 193 194 195 #define REG_CPU_MGQ_INFORMATION 0x041C 196 #define REG_FWHW_TXQ_CTRL 0x0420 197 #define REG_HWSEQ_CTRL 0x0423 198 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 199 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 200 #define REG_MULTI_BCNQ_EN 0x0426 201 #define REG_MULTI_BCNQ_OFFSET 0x0427 202 #define REG_SPEC_SIFS 0x0428 203 #define REG_RL 0x042A 204 #define REG_DARFRC 0x0430 205 #define REG_RARFRC 0x0438 206 #define REG_RRSR 0x0440 207 #define REG_ARFR0 0x0444 208 #define REG_ARFR1 0x0448 209 #define REG_ARFR2 0x044C 210 #define REG_ARFR3 0x0450 211 #define REG_AGGLEN_LMT 0x0458 212 #define REG_AMPDU_MIN_SPACE 0x045C 213 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 214 #define REG_FAST_EDCA_CTRL 0x0460 215 #define REG_RD_RESP_PKT_TH 0x0463 216 #define REG_INIRTS_RATE_SEL 0x0480 217 #define REG_INIDATA_RATE_SEL 0x0484 218 #define REG_POWER_STATUS 0x04A4 219 #define REG_POWER_STAGE1 0x04B4 220 #define REG_POWER_STAGE2 0x04B8 221 #define REG_PKT_LIFE_TIME 0x04C0 222 #define REG_STBC_SETTING 0x04C4 223 #define REG_PROT_MODE_CTRL 0x04C8 224 #define REG_MAX_AGGR_NUM 0x04CA 225 #define REG_RTS_MAX_AGGR_NUM 0x04CB 226 #define REG_BAR_MODE_CTRL 0x04CC 227 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF 228 #define REG_EARLY_MODE_CONTROL 0x4D0 229 #define REG_NQOS_SEQ 0x04DC 230 #define REG_QOS_SEQ 0x04DE 231 #define REG_NEED_CPU_HANDLE 0x04E0 232 #define REG_PKT_LOSE_RPT 0x04E1 233 #define REG_PTCL_ERR_STATUS 0x04E2 234 #define REG_DUMMY 0x04FC 235 236 /* ----------------------------------------------------- */ 237 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 238 /* ----------------------------------------------------- */ 239 #define REG_EDCA_VO_PARAM 0x0500 240 #define REG_EDCA_VI_PARAM 0x0504 241 #define REG_EDCA_BE_PARAM 0x0508 242 #define REG_EDCA_BK_PARAM 0x050C 243 #define REG_BCNTCFG 0x0510 244 #define REG_PIFS 0x0512 245 #define REG_RDG_PIFS 0x0513 246 #define REG_SIFS_CTX 0x0514 247 #define REG_SIFS_TRX 0x0516 248 #define REG_AGGR_BREAK_TIME 0x051A 249 #define REG_SLOT 0x051B 250 #define REG_TX_PTCL_CTRL 0x0520 251 #define REG_TXPAUSE 0x0522 252 #define REG_DIS_TXREQ_CLR 0x0523 253 #define REG_RD_CTRL 0x0524 254 #define REG_TBTT_PROHIBIT 0x0540 255 #define REG_RD_NAV_NXT 0x0544 256 #define REG_NAV_PROT_LEN 0x0546 257 #define REG_BCN_CTRL 0x0550 258 #define REG_MBID_NUM 0x0552 259 #define REG_DUAL_TSF_RST 0x0553 260 #define REG_BCN_INTERVAL 0x0554 261 #define REG_MBSSID_BCN_SPACE 0x0554 262 #define REG_DRVERLYINT 0x0558 263 #define REG_BCNDMATIM 0x0559 264 #define REG_ATIMWND 0x055A 265 #define REG_USTIME_TSF 0x055C 266 #define REG_BCN_MAX_ERR 0x055D 267 #define REG_RXTSF_OFFSET_CCK 0x055E 268 #define REG_RXTSF_OFFSET_OFDM 0x055F 269 #define REG_TSFTR 0x0560 270 #define REG_INIT_TSFTR 0x0564 271 #define REG_PSTIMER 0x0580 272 #define REG_TIMER0 0x0584 273 #define REG_TIMER1 0x0588 274 #define REG_ACMHWCTRL 0x05C0 275 #define REG_ACMRSTCTRL 0x05C1 276 #define REG_ACMAVG 0x05C2 277 #define REG_VO_ADMTIME 0x05C4 278 #define REG_VI_ADMTIME 0x05C6 279 #define REG_BE_ADMTIME 0x05C8 280 #define REG_EDCA_RANDOM_GEN 0x05CC 281 #define REG_SCH_TXCMD 0x05D0 282 283 /* Dual MAC Co-Existence Register */ 284 #define REG_DMC 0x05F0 285 286 /* ----------------------------------------------------- */ 287 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 288 /* ----------------------------------------------------- */ 289 #define REG_APSD_CTRL 0x0600 290 #define REG_BWOPMODE 0x0603 291 #define REG_TCR 0x0604 292 #define REG_RCR 0x0608 293 #define REG_RX_PKT_LIMIT 0x060C 294 #define REG_RX_DLK_TIME 0x060D 295 #define REG_RX_DRVINFO_SZ 0x060F 296 297 #define REG_MACID 0x0610 298 #define REG_BSSID 0x0618 299 #define REG_MAR 0x0620 300 #define REG_MBIDCAMCFG 0x0628 301 302 #define REG_USTIME_EDCA 0x0638 303 #define REG_MAC_SPEC_SIFS 0x063A 304 #define REG_RESP_SIFS_CCK 0x063C 305 #define REG_RESP_SIFS_OFDM 0x063E 306 #define REG_ACKTO 0x0640 307 #define REG_CTS2TO 0x0641 308 #define REG_EIFS 0x0642 309 310 311 /* WMA, BA, CCX */ 312 #define REG_NAV_CTRL 0x0650 313 #define REG_BACAMCMD 0x0654 314 #define REG_BACAMCONTENT 0x0658 315 #define REG_LBDLY 0x0660 316 #define REG_FWDLY 0x0661 317 #define REG_RXERR_RPT 0x0664 318 #define REG_WMAC_TRXPTCL_CTL 0x0668 319 320 321 /* Security */ 322 #define REG_CAMCMD 0x0670 323 #define REG_CAMWRITE 0x0674 324 #define REG_CAMREAD 0x0678 325 #define REG_CAMDBG 0x067C 326 #define REG_SECCFG 0x0680 327 328 /* Power */ 329 #define REG_WOW_CTRL 0x0690 330 #define REG_PSSTATUS 0x0691 331 #define REG_PS_RX_INFO 0x0692 332 #define REG_LPNAV_CTRL 0x0694 333 #define REG_WKFMCAM_CMD 0x0698 334 #define REG_WKFMCAM_RWD 0x069C 335 #define REG_RXFLTMAP0 0x06A0 336 #define REG_RXFLTMAP1 0x06A2 337 #define REG_RXFLTMAP2 0x06A4 338 #define REG_BCN_PSR_RPT 0x06A8 339 #define REG_CALB32K_CTRL 0x06AC 340 #define REG_PKT_MON_CTRL 0x06B4 341 #define REG_BT_COEX_TABLE 0x06C0 342 #define REG_WMAC_RESP_TXINFO 0x06D8 343 344 345 /* ----------------------------------------------------- */ 346 /* Redifine 8192C register definition for compatibility */ 347 /* ----------------------------------------------------- */ 348 #define CR9346 REG_9346CR 349 #define MSR (REG_CR + 2) 350 #define ISR REG_HISR 351 #define TSFR REG_TSFTR 352 353 #define MACIDR0 REG_MACID 354 #define MACIDR4 (REG_MACID + 4) 355 356 #define PBP REG_PBP 357 358 #define IDR0 MACIDR0 359 #define IDR4 MACIDR4 360 361 /* ----------------------------------------------------- */ 362 /* 8192C (MSR) Media Status Register(Offset 0x4C, 8 bits)*/ 363 /* ----------------------------------------------------- */ 364 #define MSR_NOLINK 0x00 365 #define MSR_ADHOC 0x01 366 #define MSR_INFRA 0x02 367 #define MSR_AP 0x03 368 #define MSR_MASK 0x03 369 370 /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ 371 /* ----------------------------------------------------- */ 372 /* 8192C Response Rate Set Register(offset 0x181, 24bits)*/ 373 /* ----------------------------------------------------- */ 374 #define RRSR_RSC_OFFSET 21 375 #define RRSR_SHORT_OFFSET 23 376 #define RRSR_RSC_BW_40M 0x600000 377 #define RRSR_RSC_UPSUBCHNL 0x400000 378 #define RRSR_RSC_LOWSUBCHNL 0x200000 379 #define RRSR_SHORT 0x800000 380 #define RRSR_1M BIT0 381 #define RRSR_2M BIT1 382 #define RRSR_5_5M BIT2 383 #define RRSR_11M BIT3 384 #define RRSR_6M BIT4 385 #define RRSR_9M BIT5 386 #define RRSR_12M BIT6 387 #define RRSR_18M BIT7 388 #define RRSR_24M BIT8 389 #define RRSR_36M BIT9 390 #define RRSR_48M BIT10 391 #define RRSR_54M BIT11 392 #define RRSR_MCS0 BIT12 393 #define RRSR_MCS1 BIT13 394 #define RRSR_MCS2 BIT14 395 #define RRSR_MCS3 BIT15 396 #define RRSR_MCS4 BIT16 397 #define RRSR_MCS5 BIT17 398 #define RRSR_MCS6 BIT18 399 #define RRSR_MCS7 BIT19 400 #define BRSR_ACKSHORTPMB BIT23 401 402 /* ----------------------------------------------------- */ 403 /* 8192C Rate Definition */ 404 /* ----------------------------------------------------- */ 405 /* CCK */ 406 #define RATR_1M 0x00000001 407 #define RATR_2M 0x00000002 408 #define RATR_55M 0x00000004 409 #define RATR_11M 0x00000008 410 /* OFDM */ 411 #define RATR_6M 0x00000010 412 #define RATR_9M 0x00000020 413 #define RATR_12M 0x00000040 414 #define RATR_18M 0x00000080 415 #define RATR_24M 0x00000100 416 #define RATR_36M 0x00000200 417 #define RATR_48M 0x00000400 418 #define RATR_54M 0x00000800 419 /* MCS 1 Spatial Stream */ 420 #define RATR_MCS0 0x00001000 421 #define RATR_MCS1 0x00002000 422 #define RATR_MCS2 0x00004000 423 #define RATR_MCS3 0x00008000 424 #define RATR_MCS4 0x00010000 425 #define RATR_MCS5 0x00020000 426 #define RATR_MCS6 0x00040000 427 #define RATR_MCS7 0x00080000 428 /* MCS 2 Spatial Stream */ 429 #define RATR_MCS8 0x00100000 430 #define RATR_MCS9 0x00200000 431 #define RATR_MCS10 0x00400000 432 #define RATR_MCS11 0x00800000 433 #define RATR_MCS12 0x01000000 434 #define RATR_MCS13 0x02000000 435 #define RATR_MCS14 0x04000000 436 #define RATR_MCS15 0x08000000 437 438 /* CCK */ 439 #define RATE_1M BIT(0) 440 #define RATE_2M BIT(1) 441 #define RATE_5_5M BIT(2) 442 #define RATE_11M BIT(3) 443 /* OFDM */ 444 #define RATE_6M BIT(4) 445 #define RATE_9M BIT(5) 446 #define RATE_12M BIT(6) 447 #define RATE_18M BIT(7) 448 #define RATE_24M BIT(8) 449 #define RATE_36M BIT(9) 450 #define RATE_48M BIT(10) 451 #define RATE_54M BIT(11) 452 /* MCS 1 Spatial Stream */ 453 #define RATE_MCS0 BIT(12) 454 #define RATE_MCS1 BIT(13) 455 #define RATE_MCS2 BIT(14) 456 #define RATE_MCS3 BIT(15) 457 #define RATE_MCS4 BIT(16) 458 #define RATE_MCS5 BIT(17) 459 #define RATE_MCS6 BIT(18) 460 #define RATE_MCS7 BIT(19) 461 /* MCS 2 Spatial Stream */ 462 #define RATE_MCS8 BIT(20) 463 #define RATE_MCS9 BIT(21) 464 #define RATE_MCS10 BIT(22) 465 #define RATE_MCS11 BIT(23) 466 #define RATE_MCS12 BIT(24) 467 #define RATE_MCS13 BIT(25) 468 #define RATE_MCS14 BIT(26) 469 #define RATE_MCS15 BIT(27) 470 471 /* ALL CCK Rate */ 472 #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \ 473 RATR_11M) 474 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \ 475 RATR_18M | RATR_24M | \ 476 RATR_36M | RATR_48M | RATR_54M) 477 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 478 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 479 RATR_MCS6 | RATR_MCS7) 480 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 481 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 482 RATR_MCS14 | RATR_MCS15) 483 484 /* ----------------------------------------------------- */ 485 /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ 486 /* ----------------------------------------------------- */ 487 #define BW_OPMODE_20MHZ BIT(2) 488 #define BW_OPMODE_5G BIT(1) 489 #define BW_OPMODE_11J BIT(0) 490 491 492 /* ----------------------------------------------------- */ 493 /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ 494 /* ----------------------------------------------------- */ 495 #define CAM_VALID BIT(15) 496 #define CAM_NOTVALID 0x0000 497 #define CAM_USEDK BIT(5) 498 499 #define CAM_NONE 0x0 500 #define CAM_WEP40 0x01 501 #define CAM_TKIP 0x02 502 #define CAM_AES 0x04 503 #define CAM_WEP104 0x05 504 #define CAM_SMS4 0x6 505 506 507 #define TOTAL_CAM_ENTRY 32 508 #define HALF_CAM_ENTRY 16 509 510 #define CAM_WRITE BIT(16) 511 #define CAM_READ 0x00000000 512 #define CAM_POLLINIG BIT(31) 513 514 /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ 515 #define WOW_PMEN BIT0 /* Power management Enable. */ 516 #define WOW_WOMEN BIT1 /* WoW function on or off. */ 517 #define WOW_MAGIC BIT2 /* Magic packet */ 518 #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 519 520 /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ 521 /* ----------------------------------------------------- */ 522 /* 8190 IMR/ISR bits (offset 0xfd, 8bits) */ 523 /* ----------------------------------------------------- */ 524 #define IMR8190_DISABLED 0x0 525 #define IMR_BCNDMAINT6 BIT(31) 526 #define IMR_BCNDMAINT5 BIT(30) 527 #define IMR_BCNDMAINT4 BIT(29) 528 #define IMR_BCNDMAINT3 BIT(28) 529 #define IMR_BCNDMAINT2 BIT(27) 530 #define IMR_BCNDMAINT1 BIT(26) 531 #define IMR_BCNDOK8 BIT(25) 532 #define IMR_BCNDOK7 BIT(24) 533 #define IMR_BCNDOK6 BIT(23) 534 #define IMR_BCNDOK5 BIT(22) 535 #define IMR_BCNDOK4 BIT(21) 536 #define IMR_BCNDOK3 BIT(20) 537 #define IMR_BCNDOK2 BIT(19) 538 #define IMR_BCNDOK1 BIT(18) 539 #define IMR_TIMEOUT2 BIT(17) 540 #define IMR_TIMEOUT1 BIT(16) 541 #define IMR_TXFOVW BIT(15) 542 #define IMR_PSTIMEOUT BIT(14) 543 #define IMR_BCNINT BIT(13) 544 #define IMR_RXFOVW BIT(12) 545 #define IMR_RDU BIT(11) 546 #define IMR_ATIMEND BIT(10) 547 #define IMR_BDOK BIT(9) 548 #define IMR_HIGHDOK BIT(8) 549 #define IMR_TBDOK BIT(7) 550 #define IMR_MGNTDOK BIT(6) 551 #define IMR_TBDER BIT(5) 552 #define IMR_BKDOK BIT(4) 553 #define IMR_BEDOK BIT(3) 554 #define IMR_VIDOK BIT(2) 555 #define IMR_VODOK BIT(1) 556 #define IMR_ROK BIT(0) 557 558 #define IMR_TXERR BIT(11) 559 #define IMR_RXERR BIT(10) 560 #define IMR_C2HCMD BIT(9) 561 #define IMR_CPWM BIT(8) 562 #define IMR_OCPINT BIT(1) 563 #define IMR_WLANOFF BIT(0) 564 565 /* ----------------------------------------------------- */ 566 /* 8192C EFUSE */ 567 /* ----------------------------------------------------- */ 568 #define HWSET_MAX_SIZE 256 569 #define EFUSE_MAX_SECTION 32 570 #define EFUSE_REAL_CONTENT_LEN 512 571 572 /* ----------------------------------------------------- */ 573 /* 8192C EEPROM/EFUSE share register definition. */ 574 /* ----------------------------------------------------- */ 575 #define EEPROM_DEFAULT_TSSI 0x0 576 #define EEPROM_DEFAULT_CRYSTALCAP 0x0 577 #define EEPROM_DEFAULT_THERMALMETER 0x12 578 579 #define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C 580 #define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22 581 582 #define EEPROM_DEFAULT_HT40_2SDIFF 0x0 583 /* HT20<->40 default Tx Power Index Difference */ 584 #define EEPROM_DEFAULT_HT20_DIFF 2 585 /* OFDM Tx Power index diff */ 586 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4 587 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 588 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 589 590 #define EEPROM_CHANNEL_PLAN_FCC 0x0 591 #define EEPROM_CHANNEL_PLAN_IC 0x1 592 #define EEPROM_CHANNEL_PLAN_ETSI 0x2 593 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 594 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 595 #define EEPROM_CHANNEL_PLAN_MKK 0x5 596 #define EEPROM_CHANNEL_PLAN_MKK1 0x6 597 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 598 #define EEPROM_CHANNEL_PLAN_TELEC 0x8 599 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 600 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 601 #define EEPROM_CHANNEL_PLAN_NCC 0xB 602 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 603 604 #define EEPROM_CID_DEFAULT 0x0 605 #define EEPROM_CID_TOSHIBA 0x4 606 #define EEPROM_CID_CCX 0x10 607 #define EEPROM_CID_QMI 0x0D 608 #define EEPROM_CID_WHQL 0xFE 609 610 611 #define RTL8192_EEPROM_ID 0x8129 612 #define EEPROM_WAPI_SUPPORT 0x78 613 614 615 #define RTL8190_EEPROM_ID 0x8129 /* 0-1 */ 616 #define EEPROM_HPON 0x02 /* LDO settings.2-5 */ 617 #define EEPROM_CLK 0x06 /* Clock settings.6-7 */ 618 #define EEPROM_MAC_FUNCTION 0x08 /* SE Test mode.8 */ 619 620 #define EEPROM_VID 0x28 /* SE Vendor ID.A-B */ 621 #define EEPROM_DID 0x2A /* SE Device ID. C-D */ 622 #define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */ 623 #define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */ 624 625 #define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */ 626 #define EEPROM_MAC_ADDR_MAC0_92D 0x55 627 #define EEPROM_MAC_ADDR_MAC1_92D 0x5B 628 629 /* 2.4G band Tx power index setting */ 630 #define EEPROM_CCK_TX_PWR_INX_2G 0x61 631 #define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 632 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D 633 #define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 634 #define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 635 #define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 636 #define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 637 638 /*5GL channel 32-64 */ 639 #define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C 640 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 641 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 642 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 643 #define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B 644 #define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E 645 646 /* 5GM channel 100-140 */ 647 #define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 648 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 649 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A 650 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D 651 #define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 652 #define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 653 654 /* 5GH channel 149-165 */ 655 #define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 656 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC 657 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF 658 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 659 #define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 660 #define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 661 662 /* Map of supported channels. */ 663 #define EEPROM_CHANNEL_PLAN 0xBB 664 #define EEPROM_IQK_DELTA 0xBC 665 #define EEPROM_LCK_DELTA 0xBC 666 #define EEPROM_XTAL_K 0xBD /* [7:5] */ 667 #define EEPROM_TSSI_A_5G 0xBE 668 #define EEPROM_TSSI_B_5G 0xBF 669 #define EEPROM_TSSI_AB_5G 0xC0 670 #define EEPROM_THERMAL_METER 0xC3 /* [4:0] */ 671 #define EEPROM_RF_OPT1 0xC4 672 #define EEPROM_RF_OPT2 0xC5 673 #define EEPROM_RF_OPT3 0xC6 674 #define EEPROM_RF_OPT4 0xC7 675 #define EEPROM_RF_OPT5 0xC8 676 #define EEPROM_RF_OPT6 0xC9 677 #define EEPROM_VERSION 0xCA 678 #define EEPROM_CUSTOMER_ID 0xCB 679 #define EEPROM_RF_OPT7 0xCC 680 681 #define EEPROM_DEF_PART_NO 0x3FD /* Byte */ 682 #define EEPROME_CHIP_VERSION_L 0x3FF 683 #define EEPROME_CHIP_VERSION_H 0x3FE 684 685 /* 686 * Current IOREG MAP 687 * 0x0000h ~ 0x00FFh System Configuration (256 Bytes) 688 * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 689 * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 690 * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 691 * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 692 * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 693 * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 694 * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 695 * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 696 */ 697 698 /* ----------------------------------------------------- */ 699 /* 8192C (RCR) (Offset 0x608, 32 bits) */ 700 /* ----------------------------------------------------- */ 701 #define RCR_APPFCS BIT(31) 702 #define RCR_APP_MIC BIT(30) 703 #define RCR_APP_ICV BIT(29) 704 #define RCR_APP_PHYST_RXFF BIT(28) 705 #define RCR_APP_BA_SSN BIT(27) 706 #define RCR_ENMBID BIT(24) 707 #define RCR_LSIGEN BIT(23) 708 #define RCR_MFBEN BIT(22) 709 #define RCR_HTC_LOC_CTRL BIT(14) 710 #define RCR_AMF BIT(13) 711 #define RCR_ACF BIT(12) 712 #define RCR_ADF BIT(11) 713 #define RCR_AICV BIT(9) 714 #define RCR_ACRC32 BIT(8) 715 #define RCR_CBSSID_BCN BIT(7) 716 #define RCR_CBSSID_DATA BIT(6) 717 #define RCR_APWRMGT BIT(5) 718 #define RCR_ADD3 BIT(4) 719 #define RCR_AB BIT(3) 720 #define RCR_AM BIT(2) 721 #define RCR_APM BIT(1) 722 #define RCR_AAP BIT(0) 723 #define RCR_MXDMA_OFFSET 8 724 #define RCR_FIFO_OFFSET 13 725 726 /* ----------------------------------------------------- */ 727 /* 8192C Regsiter Bit and Content definition */ 728 /* ----------------------------------------------------- */ 729 /* ----------------------------------------------------- */ 730 /* 0x0000h ~ 0x00FFh System Configuration */ 731 /* ----------------------------------------------------- */ 732 733 /* SPS0_CTRL */ 734 #define SW18_FPWM BIT(3) 735 736 737 /* SYS_ISO_CTRL */ 738 #define ISO_MD2PP BIT(0) 739 #define ISO_UA2USB BIT(1) 740 #define ISO_UD2CORE BIT(2) 741 #define ISO_PA2PCIE BIT(3) 742 #define ISO_PD2CORE BIT(4) 743 #define ISO_IP2MAC BIT(5) 744 #define ISO_DIOP BIT(6) 745 #define ISO_DIOE BIT(7) 746 #define ISO_EB2CORE BIT(8) 747 #define ISO_DIOR BIT(9) 748 749 #define PWC_EV25V BIT(14) 750 #define PWC_EV12V BIT(15) 751 752 753 /* SYS_FUNC_EN */ 754 #define FEN_BBRSTB BIT(0) 755 #define FEN_BB_GLB_RSTn BIT(1) 756 #define FEN_USBA BIT(2) 757 #define FEN_UPLL BIT(3) 758 #define FEN_USBD BIT(4) 759 #define FEN_DIO_PCIE BIT(5) 760 #define FEN_PCIEA BIT(6) 761 #define FEN_PPLL BIT(7) 762 #define FEN_PCIED BIT(8) 763 #define FEN_DIOE BIT(9) 764 #define FEN_CPUEN BIT(10) 765 #define FEN_DCORE BIT(11) 766 #define FEN_ELDR BIT(12) 767 #define FEN_DIO_RF BIT(13) 768 #define FEN_HWPDN BIT(14) 769 #define FEN_MREGEN BIT(15) 770 771 /* APS_FSMCO */ 772 #define PFM_LDALL BIT(0) 773 #define PFM_ALDN BIT(1) 774 #define PFM_LDKP BIT(2) 775 #define PFM_WOWL BIT(3) 776 #define EnPDN BIT(4) 777 #define PDN_PL BIT(5) 778 #define APFM_ONMAC BIT(8) 779 #define APFM_OFF BIT(9) 780 #define APFM_RSM BIT(10) 781 #define AFSM_HSUS BIT(11) 782 #define AFSM_PCIE BIT(12) 783 #define APDM_MAC BIT(13) 784 #define APDM_HOST BIT(14) 785 #define APDM_HPDN BIT(15) 786 #define RDY_MACON BIT(16) 787 #define SUS_HOST BIT(17) 788 #define ROP_ALD BIT(20) 789 #define ROP_PWR BIT(21) 790 #define ROP_SPS BIT(22) 791 #define SOP_MRST BIT(25) 792 #define SOP_FUSE BIT(26) 793 #define SOP_ABG BIT(27) 794 #define SOP_AMB BIT(28) 795 #define SOP_RCK BIT(29) 796 #define SOP_A8M BIT(30) 797 #define XOP_BTCK BIT(31) 798 799 /* SYS_CLKR */ 800 #define ANAD16V_EN BIT(0) 801 #define ANA8M BIT(1) 802 #define MACSLP BIT(4) 803 #define LOADER_CLK_EN BIT(5) 804 #define _80M_SSC_DIS BIT(7) 805 #define _80M_SSC_EN_HO BIT(8) 806 #define PHY_SSC_RSTB BIT(9) 807 #define SEC_CLK_EN BIT(10) 808 #define MAC_CLK_EN BIT(11) 809 #define SYS_CLK_EN BIT(12) 810 #define RING_CLK_EN BIT(13) 811 812 813 /* 9346CR */ 814 #define BOOT_FROM_EEPROM BIT(4) 815 #define EEPROM_EN BIT(5) 816 817 /* AFE_MISC */ 818 #define AFE_BGEN BIT(0) 819 #define AFE_MBEN BIT(1) 820 #define MAC_ID_EN BIT(7) 821 822 /* RSV_CTRL */ 823 #define WLOCK_ALL BIT(0) 824 #define WLOCK_00 BIT(1) 825 #define WLOCK_04 BIT(2) 826 #define WLOCK_08 BIT(3) 827 #define WLOCK_40 BIT(4) 828 #define R_DIS_PRST_0 BIT(5) 829 #define R_DIS_PRST_1 BIT(6) 830 #define LOCK_ALL_EN BIT(7) 831 832 /* RF_CTRL */ 833 #define RF_EN BIT(0) 834 #define RF_RSTB BIT(1) 835 #define RF_SDMRSTB BIT(2) 836 837 838 839 /* LDOA15_CTRL */ 840 #define LDA15_EN BIT(0) 841 #define LDA15_STBY BIT(1) 842 #define LDA15_OBUF BIT(2) 843 #define LDA15_REG_VOS BIT(3) 844 #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 845 846 847 848 /* LDOV12D_CTRL */ 849 #define LDV12_EN BIT(0) 850 #define LDV12_SDBY BIT(1) 851 #define LPLDO_HSM BIT(2) 852 #define LPLDO_LSM_DIS BIT(3) 853 #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 854 855 856 /* AFE_XTAL_CTRL */ 857 #define XTAL_EN BIT(0) 858 #define XTAL_BSEL BIT(1) 859 #define _XTAL_BOSC(x) (((x) & 0x3) << 2) 860 #define _XTAL_CADJ(x) (((x) & 0xF) << 4) 861 #define XTAL_GATE_USB BIT(8) 862 #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 863 #define XTAL_GATE_AFE BIT(11) 864 #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 865 #define XTAL_RF_GATE BIT(14) 866 #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 867 #define XTAL_GATE_DIG BIT(17) 868 #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 869 #define XTAL_BT_GATE BIT(20) 870 #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 871 #define _XTAL_GPIO(x) (((x) & 0x7) << 23) 872 873 874 #define CKDLY_AFE BIT(26) 875 #define CKDLY_USB BIT(27) 876 #define CKDLY_DIG BIT(28) 877 #define CKDLY_BT BIT(29) 878 879 880 /* AFE_PLL_CTRL */ 881 #define APLL_EN BIT(0) 882 #define APLL_320_EN BIT(1) 883 #define APLL_FREF_SEL BIT(2) 884 #define APLL_EDGE_SEL BIT(3) 885 #define APLL_WDOGB BIT(4) 886 #define APLL_LPFEN BIT(5) 887 888 #define APLL_REF_CLK_13MHZ 0x1 889 #define APLL_REF_CLK_19_2MHZ 0x2 890 #define APLL_REF_CLK_20MHZ 0x3 891 #define APLL_REF_CLK_25MHZ 0x4 892 #define APLL_REF_CLK_26MHZ 0x5 893 #define APLL_REF_CLK_38_4MHZ 0x6 894 #define APLL_REF_CLK_40MHZ 0x7 895 896 #define APLL_320EN BIT(14) 897 #define APLL_80EN BIT(15) 898 #define APLL_1MEN BIT(24) 899 900 901 /* EFUSE_CTRL */ 902 #define ALD_EN BIT(18) 903 #define EF_PD BIT(19) 904 #define EF_FLAG BIT(31) 905 906 /* EFUSE_TEST */ 907 #define EF_TRPT BIT(7) 908 #define LDOE25_EN BIT(31) 909 910 /* MCUFWDL */ 911 #define MCUFWDL_EN BIT(0) 912 #define MCUFWDL_RDY BIT(1) 913 #define FWDL_ChkSum_rpt BIT(2) 914 #define MACINI_RDY BIT(3) 915 #define BBINI_RDY BIT(4) 916 #define RFINI_RDY BIT(5) 917 #define WINTINI_RDY BIT(6) 918 #define MAC1_WINTINI_RDY BIT(11) 919 #define CPRST BIT(23) 920 921 /* REG_SYS_CFG */ 922 #define XCLK_VLD BIT(0) 923 #define ACLK_VLD BIT(1) 924 #define UCLK_VLD BIT(2) 925 #define PCLK_VLD BIT(3) 926 #define PCIRSTB BIT(4) 927 #define V15_VLD BIT(5) 928 #define TRP_B15V_EN BIT(7) 929 #define SIC_IDLE BIT(8) 930 #define BD_MAC2 BIT(9) 931 #define BD_MAC1 BIT(10) 932 #define IC_MACPHY_MODE BIT(11) 933 #define PAD_HWPD_IDN BIT(22) 934 #define TRP_VAUX_EN BIT(23) 935 #define TRP_BT_EN BIT(24) 936 #define BD_PKG_SEL BIT(25) 937 #define BD_HCI_SEL BIT(26) 938 #define TYPE_ID BIT(27) 939 940 /* LLT_INIT */ 941 #define _LLT_NO_ACTIVE 0x0 942 #define _LLT_WRITE_ACCESS 0x1 943 #define _LLT_READ_ACCESS 0x2 944 945 #define _LLT_INIT_DATA(x) ((x) & 0xFF) 946 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 947 #define _LLT_OP(x) (((x) & 0x3) << 30) 948 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 949 950 951 /* ----------------------------------------------------- */ 952 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 953 /* ----------------------------------------------------- */ 954 #define RETRY_LIMIT_SHORT_SHIFT 8 955 #define RETRY_LIMIT_LONG_SHIFT 0 956 957 958 /* ----------------------------------------------------- */ 959 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 960 /* ----------------------------------------------------- */ 961 /* EDCA setting */ 962 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 963 #define AC_PARAM_ECW_MAX_OFFSET 12 964 #define AC_PARAM_ECW_MIN_OFFSET 8 965 #define AC_PARAM_AIFS_OFFSET 0 966 967 /* ACMHWCTRL */ 968 #define ACMHW_HWEN BIT(0) 969 #define ACMHW_BEQEN BIT(1) 970 #define ACMHW_VIQEN BIT(2) 971 #define ACMHW_VOQEN BIT(3) 972 973 /* ----------------------------------------------------- */ 974 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 975 /* ----------------------------------------------------- */ 976 977 /* TCR */ 978 #define TSFRST BIT(0) 979 #define DIS_GCLK BIT(1) 980 #define PAD_SEL BIT(2) 981 #define PWR_ST BIT(6) 982 #define PWRBIT_OW_EN BIT(7) 983 #define ACRC BIT(8) 984 #define CFENDFORM BIT(9) 985 #define ICV BIT(10) 986 987 /* SECCFG */ 988 #define SCR_TXUSEDK BIT(0) 989 #define SCR_RXUSEDK BIT(1) 990 #define SCR_TXENCENABLE BIT(2) 991 #define SCR_RXENCENABLE BIT(3) 992 #define SCR_SKBYA2 BIT(4) 993 #define SCR_NOSKMC BIT(5) 994 #define SCR_TXBCUSEDK BIT(6) 995 #define SCR_RXBCUSEDK BIT(7) 996 997 /* General definitions */ 998 #define LAST_ENTRY_OF_TX_PKT_BUFFER 255 999 #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 1000 1001 #define POLLING_LLT_THRESHOLD 20 1002 #define POLLING_READY_TIMEOUT_COUNT 1000 1003 1004 /* Min Spacing related settings. */ 1005 #define MAX_MSS_DENSITY_2T 0x13 1006 #define MAX_MSS_DENSITY_1T 0x0A 1007 1008 1009 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 1010 /* 1. PMAC duplicate register due to connection: */ 1011 /* RF_Mode, TRxRN, NumOf L-STF */ 1012 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 1013 /* 3. RF register 0x00-2E */ 1014 /* 4. Bit Mask for BB/RF register */ 1015 /* 5. Other defintion for BB/RF R/W */ 1016 1017 /* 3. Page8(0x800) */ 1018 #define RFPGA0_RFMOD 0x800 1019 1020 #define RFPGA0_TXINFO 0x804 1021 #define RFPGA0_PSDFUNCTION 0x808 1022 1023 #define RFPGA0_TXGAINSTAGE 0x80c 1024 1025 #define RFPGA0_RFTIMING1 0x810 1026 #define RFPGA0_RFTIMING2 0x814 1027 1028 #define RFPGA0_XA_HSSIPARAMETER1 0x820 1029 #define RFPGA0_XA_HSSIPARAMETER2 0x824 1030 #define RFPGA0_XB_HSSIPARAMETER1 0x828 1031 #define RFPGA0_XB_HSSIPARAMETER2 0x82c 1032 1033 #define RFPGA0_XA_LSSIPARAMETER 0x840 1034 #define RFPGA0_XB_LSSIPARAMETER 0x844 1035 1036 #define RFPGA0_RFWAkEUPPARAMETER 0x850 1037 #define RFPGA0_RFSLEEPUPPARAMETER 0x854 1038 1039 #define RFPGA0_XAB_SWITCHCONTROL 0x858 1040 #define RFPGA0_XCD_SWITCHCONTROL 0x85c 1041 1042 #define RFPGA0_XA_RFINTERFACEOE 0x860 1043 #define RFPGA0_XB_RFINTERFACEOE 0x864 1044 1045 #define RFPGA0_XAB_RFINTERFACESW 0x870 1046 #define RFPGA0_XCD_RFINTERFACESW 0x874 1047 1048 #define RFPGA0_XAB_RFPARAMETER 0x878 1049 #define RFPGA0_XCD_RFPARAMETER 0x87c 1050 1051 #define RFPGA0_ANALOGPARAMETER1 0x880 1052 #define RFPGA0_ANALOGPARAMETER2 0x884 1053 #define RFPGA0_ANALOGPARAMETER3 0x888 1054 #define RFPGA0_ADDALLOCKEN 0x888 1055 #define RFPGA0_ANALOGPARAMETER4 0x88c 1056 1057 #define RFPGA0_XA_LSSIREADBACK 0x8a0 1058 #define RFPGA0_XB_LSSIREADBACK 0x8a4 1059 #define RFPGA0_XC_LSSIREADBACK 0x8a8 1060 #define RFPGA0_XD_LSSIREADBACK 0x8ac 1061 1062 #define RFPGA0_PSDREPORT 0x8b4 1063 #define TRANSCEIVERA_HSPI_READBACK 0x8b8 1064 #define TRANSCEIVERB_HSPI_READBACK 0x8bc 1065 #define RFPGA0_XAB_RFINTERFACERB 0x8e0 1066 #define RFPGA0_XCD_RFINTERFACERB 0x8e4 1067 1068 /* 4. Page9(0x900) */ 1069 #define RFPGA1_RFMOD 0x900 1070 1071 #define RFPGA1_TXBLOCK 0x904 1072 #define RFPGA1_DEBUGSELECT 0x908 1073 #define RFPGA1_TXINFO 0x90c 1074 1075 /* 5. PageA(0xA00) */ 1076 #define RCCK0_SYSTEM 0xa00 1077 1078 #define RCCK0_AFESSTTING 0xa04 1079 #define RCCK0_CCA 0xa08 1080 1081 #define RCCK0_RXAGC1 0xa0c 1082 #define RCCK0_RXAGC2 0xa10 1083 1084 #define RCCK0_RXHP 0xa14 1085 1086 #define RCCK0_DSPPARAMETER1 0xa18 1087 #define RCCK0_DSPPARAMETER2 0xa1c 1088 1089 #define RCCK0_TXFILTER1 0xa20 1090 #define RCCK0_TXFILTER2 0xa24 1091 #define RCCK0_DEBUGPORT 0xa28 1092 #define RCCK0_FALSEALARMREPORT 0xa2c 1093 #define RCCK0_TRSSIREPORT 0xa50 1094 #define RCCK0_RXREPORT 0xa54 1095 #define RCCK0_FACOUNTERLOWER 0xa5c 1096 #define RCCK0_FACOUNTERUPPER 0xa58 1097 1098 /* 6. PageC(0xC00) */ 1099 #define ROFDM0_LSTF 0xc00 1100 1101 #define ROFDM0_TRXPATHENABLE 0xc04 1102 #define ROFDM0_TRMUXPAR 0xc08 1103 #define ROFDM0_TRSWISOLATION 0xc0c 1104 1105 #define ROFDM0_XARXAFE 0xc10 1106 #define ROFDM0_XARXIQIMBALANCE 0xc14 1107 #define ROFDM0_XBRXAFE 0xc18 1108 #define ROFDM0_XBRXIQIMBALANCE 0xc1c 1109 #define ROFDM0_XCRXAFE 0xc20 1110 #define ROFDM0_XCRXIQIMBALANCE 0xc24 1111 #define ROFDM0_XDRXAFE 0xc28 1112 #define ROFDM0_XDRXIQIMBALANCE 0xc2c 1113 1114 #define ROFDM0_RXDETECTOR1 0xc30 1115 #define ROFDM0_RXDETECTOR2 0xc34 1116 #define ROFDM0_RXDETECTOR3 0xc38 1117 #define ROFDM0_RXDETECTOR4 0xc3c 1118 1119 #define ROFDM0_RXDSP 0xc40 1120 #define ROFDM0_CFOANDDAGC 0xc44 1121 #define ROFDM0_CCADROPTHRESHOLD 0xc48 1122 #define ROFDM0_ECCATHRESHOLD 0xc4c 1123 1124 #define ROFDM0_XAAGCCORE1 0xc50 1125 #define ROFDM0_XAAGCCORE2 0xc54 1126 #define ROFDM0_XBAGCCORE1 0xc58 1127 #define ROFDM0_XBAGCCORE2 0xc5c 1128 #define ROFDM0_XCAGCCORE1 0xc60 1129 #define ROFDM0_XCAGCCORE2 0xc64 1130 #define ROFDM0_XDAGCCORE1 0xc68 1131 #define ROFDM0_XDAGCCORE2 0xc6c 1132 1133 #define ROFDM0_AGCPARAMETER1 0xc70 1134 #define ROFDM0_AGCPARAMETER2 0xc74 1135 #define ROFDM0_AGCRSSITABLE 0xc78 1136 #define ROFDM0_HTSTFAGC 0xc7c 1137 1138 #define ROFDM0_XATxIQIMBALANCE 0xc80 1139 #define ROFDM0_XATxAFE 0xc84 1140 #define ROFDM0_XBTxIQIMBALANCE 0xc88 1141 #define ROFDM0_XBTxAFE 0xc8c 1142 #define ROFDM0_XCTxIQIMBALANCE 0xc90 1143 #define ROFDM0_XCTxAFE 0xc94 1144 #define ROFDM0_XDTxIQIMBALANCE 0xc98 1145 #define ROFDM0_XDTxAFE 0xc9c 1146 1147 #define ROFDM0_RXHPPARAMETER 0xce0 1148 #define ROFDM0_TXPSEUDONOISEWGT 0xce4 1149 #define ROFDM0_FRAMESYNC 0xcf0 1150 #define ROFDM0_DFSREPORT 0xcf4 1151 #define ROFDM0_TXCOEFF1 0xca4 1152 #define ROFDM0_TXCOEFF2 0xca8 1153 #define ROFDM0_TXCOEFF3 0xcac 1154 #define ROFDM0_TXCOEFF4 0xcb0 1155 #define ROFDM0_TXCOEFF5 0xcb4 1156 #define ROFDM0_TXCOEFF6 0xcb8 1157 1158 /* 7. PageD(0xD00) */ 1159 #define ROFDM1_LSTF 0xd00 1160 #define ROFDM1_TRXPATHENABLE 0xd04 1161 1162 #define ROFDM1_CFO 0xd08 1163 #define ROFDM1_CSI1 0xd10 1164 #define ROFDM1_SBD 0xd14 1165 #define ROFDM1_CSI2 0xd18 1166 #define ROFDM1_CFOTRACKING 0xd2c 1167 #define ROFDM1_TRXMESAURE1 0xd34 1168 #define ROFDM1_INTFDET 0xd3c 1169 #define ROFDM1_PSEUDONOISESTATEAB 0xd50 1170 #define ROFDM1_PSEUDONOISESTATECD 0xd54 1171 #define ROFDM1_RXPSEUDONOISEWGT 0xd58 1172 1173 #define ROFDM_PHYCOUNTER1 0xda0 1174 #define ROFDM_PHYCOUNTER2 0xda4 1175 #define ROFDM_PHYCOUNTER3 0xda8 1176 1177 #define ROFDM_SHORTCFOAB 0xdac 1178 #define ROFDM_SHORTCFOCD 0xdb0 1179 #define ROFDM_LONGCFOAB 0xdb4 1180 #define ROFDM_LONGCFOCD 0xdb8 1181 #define ROFDM_TAILCFOAB 0xdbc 1182 #define ROFDM_TAILCFOCD 0xdc0 1183 #define ROFDM_PWMEASURE1 0xdc4 1184 #define ROFDM_PWMEASURE2 0xdc8 1185 #define ROFDM_BWREPORT 0xdcc 1186 #define ROFDM_AGCREPORT 0xdd0 1187 #define ROFDM_RXSNR 0xdd4 1188 #define ROFDM_RXEVMCSI 0xdd8 1189 #define ROFDM_SIGReport 0xddc 1190 1191 /* 8. PageE(0xE00) */ 1192 #define RTXAGC_A_RATE18_06 0xe00 1193 #define RTXAGC_A_RATE54_24 0xe04 1194 #define RTXAGC_A_CCK1_MCS32 0xe08 1195 #define RTXAGC_A_MCS03_MCS00 0xe10 1196 #define RTXAGC_A_MCS07_MCS04 0xe14 1197 #define RTXAGC_A_MCS11_MCS08 0xe18 1198 #define RTXAGC_A_MCS15_MCS12 0xe1c 1199 1200 #define RTXAGC_B_RATE18_06 0x830 1201 #define RTXAGC_B_RATE54_24 0x834 1202 #define RTXAGC_B_CCK1_55_MCS32 0x838 1203 #define RTXAGC_B_MCS03_MCS00 0x83c 1204 #define RTXAGC_B_MCS07_MCS04 0x848 1205 #define RTXAGC_B_MCS11_MCS08 0x84c 1206 #define RTXAGC_B_MCS15_MCS12 0x868 1207 #define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1208 1209 /* RL6052 Register definition */ 1210 #define RF_AC 0x00 1211 1212 #define RF_IQADJ_G1 0x01 1213 #define RF_IQADJ_G2 0x02 1214 #define RF_POW_TRSW 0x05 1215 1216 #define RF_GAIN_RX 0x06 1217 #define RF_GAIN_TX 0x07 1218 1219 #define RF_TXM_IDAC 0x08 1220 #define RF_BS_IQGEN 0x0F 1221 1222 #define RF_MODE1 0x10 1223 #define RF_MODE2 0x11 1224 1225 #define RF_RX_AGC_HP 0x12 1226 #define RF_TX_AGC 0x13 1227 #define RF_BIAS 0x14 1228 #define RF_IPA 0x15 1229 #define RF_POW_ABILITY 0x17 1230 #define RF_MODE_AG 0x18 1231 #define rRfChannel 0x18 1232 #define RF_CHNLBW 0x18 1233 #define RF_TOP 0x19 1234 1235 #define RF_RX_G1 0x1A 1236 #define RF_RX_G2 0x1B 1237 1238 #define RF_RX_BB2 0x1C 1239 #define RF_RX_BB1 0x1D 1240 1241 #define RF_RCK1 0x1E 1242 #define RF_RCK2 0x1F 1243 1244 #define RF_TX_G1 0x20 1245 #define RF_TX_G2 0x21 1246 #define RF_TX_G3 0x22 1247 1248 #define RF_TX_BB1 0x23 1249 1250 #define RF_T_METER 0x42 1251 1252 #define RF_SYN_G1 0x25 1253 #define RF_SYN_G2 0x26 1254 #define RF_SYN_G3 0x27 1255 #define RF_SYN_G4 0x28 1256 #define RF_SYN_G5 0x29 1257 #define RF_SYN_G6 0x2A 1258 #define RF_SYN_G7 0x2B 1259 #define RF_SYN_G8 0x2C 1260 1261 #define RF_RCK_OS 0x30 1262 1263 #define RF_TXPA_G1 0x31 1264 #define RF_TXPA_G2 0x32 1265 #define RF_TXPA_G3 0x33 1266 1267 /* Bit Mask */ 1268 1269 /* 2. Page8(0x800) */ 1270 #define BRFMOD 0x1 1271 #define BCCKTXSC 0x30 1272 #define BCCKEN 0x1000000 1273 #define BOFDMEN 0x2000000 1274 1275 #define B3WIREDATALENGTH 0x800 1276 #define B3WIREADDRESSLENGTH 0x400 1277 1278 #define BRFSI_RFENV 0x10 1279 1280 #define BLSSIREADADDRESS 0x7f800000 1281 #define BLSSIREADEDGE 0x80000000 1282 #define BLSSIREADBACKDATA 0xfffff 1283 /* 4. PageA(0xA00) */ 1284 #define BCCKSIDEBAND 0x10 1285 1286 /* Other Definition */ 1287 #define BBYTE0 0x1 1288 #define BBYTE1 0x2 1289 #define BBYTE2 0x4 1290 #define BBYTE3 0x8 1291 #define BWORD0 0x3 1292 #define BWORD1 0xc 1293 #define BDWORD 0xf 1294 1295 #endif 1296
