Searched refs:DSPCNTR (Results 1 – 8 of 8) sorted by relevance
297 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
215 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
1201 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()1267 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
1962 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()1971 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()1980 MMIO_D(DSPCNTR(PIPE_C), D_ALL); in init_generic_mmio_info()
3319 i915_reg_t reg = DSPCNTR(i9xx_plane); in i9xx_update_plane()3383 I915_WRITE_FW(DSPCNTR(i9xx_plane), 0); in i9xx_disable_plane()3388 POSTING_READ_FW(DSPCNTR(i9xx_plane)); in i9xx_disable_plane()3411 val = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()7746 val = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()15353 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()15354 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()15355 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()16094 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
1700 val = I915_READ(DSPCNTR(i9xx_plane)); in intel_dsi_get_panel_orientation()
8407 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()8408 I915_READ(DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
6162 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro
