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Searched refs:DSPCLK_GATE_D (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/gma500/
Dcdv_device.c276 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
329 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
Dpsb_intel_reg.h1311 #define DSPCLK_GATE_D 0x6200 macro
Dcdv_intel_dp.c1979 reg_value = REG_READ(DSPCLK_GATE_D); in cdv_disable_intel_clock_gating()
1988 REG_WRITE(DSPCLK_GATE_D, reg_value); in cdv_disable_intel_clock_gating()
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_i2c.c151 val = I915_READ(DSPCLK_GATE_D); in pnv_gmbus_clock_gating()
156 I915_WRITE(DSPCLK_GATE_D, val); in pnv_gmbus_clock_gating()
Dvlv_dsi.c840 val = I915_READ(DSPCLK_GATE_D); in intel_dsi_pre_enable()
842 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_pre_enable()
997 val = I915_READ(DSPCLK_GATE_D); in intel_dsi_post_disable()
999 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_post_disable()
Dintel_overlay.c199 I915_WRITE(DSPCLK_GATE_D, 0); in i830_overlay_clock_gating()
201 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); in i830_overlay_clock_gating()
Dintel_runtime_pm.c963 val = I915_READ(DSPCLK_GATE_D); in vlv_init_display_clock_gating()
966 I915_WRITE(DSPCLK_GATE_D, val); in vlv_init_display_clock_gating()
Dintel_pm.c9120 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()
9136 I915_WRITE(DSPCLK_GATE_D, 0); in i965gm_init_clock_gating()
Di915_reg.h3352 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) macro