1 /* 2 * drivers/video/mmp/hw/mmp_ctrl.h 3 * 4 * 5 * Copyright (C) 2012 Marvell Technology Group Ltd. 6 * Authors: Guoqing Li <ligq@marvell.com> 7 * Lisa Du <cldu@marvell.com> 8 * Zhou Zhu <zzhu3@marvell.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along with 21 * this program. If not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 #ifndef _MMP_CTRL_H_ 26 #define _MMP_CTRL_H_ 27 28 #include <video/mmp_disp.h> 29 30 /* ------------< LCD register >------------ */ 31 struct lcd_regs { 32 /* TV patch register for MMP2 */ 33 /* 32 bit TV Video Frame0 Y Starting Address */ 34 #define LCD_TVD_START_ADDR_Y0 (0x0000) 35 /* 32 bit TV Video Frame0 U Starting Address */ 36 #define LCD_TVD_START_ADDR_U0 (0x0004) 37 /* 32 bit TV Video Frame0 V Starting Address */ 38 #define LCD_TVD_START_ADDR_V0 (0x0008) 39 /* 32 bit TV Video Frame0 Command Starting Address */ 40 #define LCD_TVD_START_ADDR_C0 (0x000C) 41 /* 32 bit TV Video Frame1 Y Starting Address Register*/ 42 #define LCD_TVD_START_ADDR_Y1 (0x0010) 43 /* 32 bit TV Video Frame1 U Starting Address Register*/ 44 #define LCD_TVD_START_ADDR_U1 (0x0014) 45 /* 32 bit TV Video Frame1 V Starting Address Register*/ 46 #define LCD_TVD_START_ADDR_V1 (0x0018) 47 /* 32 bit TV Video Frame1 Command Starting Address Register*/ 48 #define LCD_TVD_START_ADDR_C1 (0x001C) 49 /* 32 bit TV Video Y andC Line Length(Pitch)Register*/ 50 #define LCD_TVD_PITCH_YC (0x0020) 51 /* 32 bit TV Video U andV Line Length(Pitch)Register*/ 52 #define LCD_TVD_PITCH_UV (0x0024) 53 /* 32 bit TV Video Starting Point on Screen Register*/ 54 #define LCD_TVD_OVSA_HPXL_VLN (0x0028) 55 /* 32 bit TV Video Source Size Register*/ 56 #define LCD_TVD_HPXL_VLN (0x002C) 57 /* 32 bit TV Video Destination Size (After Zooming)Register*/ 58 #define LCD_TVDZM_HPXL_VLN (0x0030) 59 u32 v_y0; 60 u32 v_u0; 61 u32 v_v0; 62 u32 v_c0; 63 u32 v_y1; 64 u32 v_u1; 65 u32 v_v1; 66 u32 v_c1; 67 u32 v_pitch_yc; /* Video Y and C Line Length (Pitch) */ 68 u32 v_pitch_uv; /* Video U and V Line Length (Pitch) */ 69 u32 v_start; /* Video Starting Point on Screen */ 70 u32 v_size; /* Video Source Size */ 71 u32 v_size_z; /* Video Destination Size (After Zooming) */ 72 73 /* 32 bit TV Graphic Frame 0 Starting Address Register*/ 74 #define LCD_TVG_START_ADDR0 (0x0034) 75 /* 32 bit TV Graphic Frame 1 Starting Address Register*/ 76 #define LCD_TVG_START_ADDR1 (0x0038) 77 /* 32 bit TV Graphic Line Length(Pitch)Register*/ 78 #define LCD_TVG_PITCH (0x003C) 79 /* 32 bit TV Graphic Starting Point on Screen Register*/ 80 #define LCD_TVG_OVSA_HPXL_VLN (0x0040) 81 /* 32 bit TV Graphic Source Size Register*/ 82 #define LCD_TVG_HPXL_VLN (0x0044) 83 /* 32 bit TV Graphic Destination size (after Zooming)Register*/ 84 #define LCD_TVGZM_HPXL_VLN (0x0048) 85 u32 g_0; /* Graphic Frame 0/1 Starting Address */ 86 u32 g_1; 87 u32 g_pitch; /* Graphic Line Length (Pitch) */ 88 u32 g_start; /* Graphic Starting Point on Screen */ 89 u32 g_size; /* Graphic Source Size */ 90 u32 g_size_z; /* Graphic Destination Size (After Zooming) */ 91 92 /* 32 bit TV Hardware Cursor Starting Point on screen Register*/ 93 #define LCD_TVC_OVSA_HPXL_VLN (0x004C) 94 /* 32 bit TV Hardware Cursor Size Register */ 95 #define LCD_TVC_HPXL_VLN (0x0050) 96 u32 hc_start; /* Hardware Cursor */ 97 u32 hc_size; /* Hardware Cursor */ 98 99 /* 32 bit TV Total Screen Size Register*/ 100 #define LCD_TV_V_H_TOTAL (0x0054) 101 /* 32 bit TV Screen Active Size Register*/ 102 #define LCD_TV_V_H_ACTIVE (0x0058) 103 /* 32 bit TV Screen Horizontal Porch Register*/ 104 #define LCD_TV_H_PORCH (0x005C) 105 /* 32 bit TV Screen Vertical Porch Register*/ 106 #define LCD_TV_V_PORCH (0x0060) 107 u32 screen_size; /* Screen Total Size */ 108 u32 screen_active; /* Screen Active Size */ 109 u32 screen_h_porch; /* Screen Horizontal Porch */ 110 u32 screen_v_porch; /* Screen Vertical Porch */ 111 112 /* 32 bit TV Screen Blank Color Register*/ 113 #define LCD_TV_BLANKCOLOR (0x0064) 114 /* 32 bit TV Hardware Cursor Color1 Register*/ 115 #define LCD_TV_ALPHA_COLOR1 (0x0068) 116 /* 32 bit TV Hardware Cursor Color2 Register*/ 117 #define LCD_TV_ALPHA_COLOR2 (0x006C) 118 u32 blank_color; /* Screen Blank Color */ 119 u32 hc_Alpha_color1; /* Hardware Cursor Color1 */ 120 u32 hc_Alpha_color2; /* Hardware Cursor Color2 */ 121 122 /* 32 bit TV Video Y Color Key Control*/ 123 #define LCD_TV_COLORKEY_Y (0x0070) 124 /* 32 bit TV Video U Color Key Control*/ 125 #define LCD_TV_COLORKEY_U (0x0074) 126 /* 32 bit TV Video V Color Key Control*/ 127 #define LCD_TV_COLORKEY_V (0x0078) 128 u32 v_colorkey_y; /* Video Y Color Key Control */ 129 u32 v_colorkey_u; /* Video U Color Key Control */ 130 u32 v_colorkey_v; /* Video V Color Key Control */ 131 132 /* 32 bit TV VSYNC PulsePixel Edge Control Register*/ 133 #define LCD_TV_SEPXLCNT (0x007C) 134 u32 vsync_ctrl; /* VSYNC PulsePixel Edge Control */ 135 }; 136 137 #define intf_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \ 138 LCD_DUMB2_CTRL) : LCD_SPU_DUMB_CTRL) 139 #define dma_ctrl0(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL0 : \ 140 LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0) 141 #define dma_ctrl1(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL1 : \ 142 LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1) 143 #define dma_ctrl(ctrl1, id) (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id)) 144 145 /* 32 bit TV Path DMA Control 0*/ 146 #define LCD_TV_CTRL0 (0x0080) 147 /* 32 bit TV Path DMA Control 1*/ 148 #define LCD_TV_CTRL1 (0x0084) 149 /* 32 bit TV Path Video Contrast*/ 150 #define LCD_TV_CONTRAST (0x0088) 151 /* 32 bit TV Path Video Saturation*/ 152 #define LCD_TV_SATURATION (0x008C) 153 /* 32 bit TV Path Video Hue Adjust*/ 154 #define LCD_TV_CBSH_HUE (0x0090) 155 /* 32 bit TV Path TVIF Control Register */ 156 #define LCD_TVIF_CTRL (0x0094) 157 #define TV_VBLNK_VALID_EN (1 << 12) 158 159 /* 32 bit TV Path I/O Pad Control*/ 160 #define LCD_TVIOPAD_CTRL (0x0098) 161 /* 32 bit TV Path Cloc Divider */ 162 #define LCD_TCLK_DIV (0x009C) 163 164 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\ 165 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV)) 166 #define intf_rbswap_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \ 167 PN2_IOPAD_CONTROL) : LCD_TOP_CTRL) 168 169 /* dither configure */ 170 #define LCD_DITHER_CTRL (0x00A0) 171 172 #define DITHER_TBL_INDEX_SEL(s) ((s) << 16) 173 #define DITHER_MODE2(m) ((m) << 12) 174 #define DITHER_MODE2_SHIFT (12) 175 #define DITHER_4X8_EN2 (1 << 9) 176 #define DITHER_4X8_EN2_SHIFT (9) 177 #define DITHER_EN2 (1 << 8) 178 #define DITHER_MODE1(m) ((m) << 4) 179 #define DITHER_MODE1_SHIFT (4) 180 #define DITHER_4X8_EN1 (1 << 1) 181 #define DITHER_4X8_EN1_SHIFT (1) 182 #define DITHER_EN1 (1) 183 184 /* dither table data was fixed by video bpp of input and output*/ 185 #define DITHER_TB_4X4_INDEX0 (0x3b19f7d5) 186 #define DITHER_TB_4X4_INDEX1 (0x082ac4e6) 187 #define DITHER_TB_4X8_INDEX0 (0xf7d508e6) 188 #define DITHER_TB_4X8_INDEX1 (0x3b194c2a) 189 #define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7) 190 #define DITHER_TB_4X8_INDEX3 (0x082a193b) 191 #define LCD_DITHER_TBL_DATA (0x00A4) 192 193 /* Video Frame 0&1 start address registers */ 194 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 195 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4 196 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8 197 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */ 198 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0 199 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4 200 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8 201 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */ 202 203 /* YC & UV Pitch */ 204 #define LCD_SPU_DMA_PITCH_YC 0x00E0 205 #define SPU_DMA_PITCH_C(c) ((c)<<16) 206 #define SPU_DMA_PITCH_Y(y) (y) 207 #define LCD_SPU_DMA_PITCH_UV 0x00E4 208 #define SPU_DMA_PITCH_V(v) ((v)<<16) 209 #define SPU_DMA_PITCH_U(u) (u) 210 211 /* Video Starting Point on Screen Register */ 212 #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8 213 #define CFG_DMA_OVSA_VLN(y) ((y)<<16) /* 0~0xfff */ 214 #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */ 215 216 /* Video Size Register */ 217 #define LCD_SPU_DMA_HPXL_VLN 0x00EC 218 #define CFG_DMA_VLN(y) ((y)<<16) 219 #define CFG_DMA_HPXL(x) (x) 220 221 /* Video Size After zooming Register */ 222 #define LCD_SPU_DZM_HPXL_VLN 0x00F0 223 #define CFG_DZM_VLN(y) ((y)<<16) 224 #define CFG_DZM_HPXL(x) (x) 225 226 /* Graphic Frame 0&1 Starting Address Register */ 227 #define LCD_CFG_GRA_START_ADDR0 0x00F4 228 #define LCD_CFG_GRA_START_ADDR1 0x00F8 229 230 /* Graphic Frame Pitch */ 231 #define LCD_CFG_GRA_PITCH 0x00FC 232 233 /* Graphic Starting Point on Screen Register */ 234 #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100 235 #define CFG_GRA_OVSA_VLN(y) ((y)<<16) 236 #define CFG_GRA_OVSA_HPXL(x) (x) 237 238 /* Graphic Size Register */ 239 #define LCD_SPU_GRA_HPXL_VLN 0x0104 240 #define CFG_GRA_VLN(y) ((y)<<16) 241 #define CFG_GRA_HPXL(x) (x) 242 243 /* Graphic Size after Zooming Register */ 244 #define LCD_SPU_GZM_HPXL_VLN 0x0108 245 #define CFG_GZM_VLN(y) ((y)<<16) 246 #define CFG_GZM_HPXL(x) (x) 247 248 /* HW Cursor Starting Point on Screen Register */ 249 #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C 250 #define CFG_HWC_OVSA_VLN(y) ((y)<<16) 251 #define CFG_HWC_OVSA_HPXL(x) (x) 252 253 /* HW Cursor Size */ 254 #define LCD_SPU_HWC_HPXL_VLN 0x0110 255 #define CFG_HWC_VLN(y) ((y)<<16) 256 #define CFG_HWC_HPXL(x) (x) 257 258 /* Total Screen Size Register */ 259 #define LCD_SPUT_V_H_TOTAL 0x0114 260 #define CFG_V_TOTAL(y) ((y)<<16) 261 #define CFG_H_TOTAL(x) (x) 262 263 /* Total Screen Active Size Register */ 264 #define LCD_SPU_V_H_ACTIVE 0x0118 265 #define CFG_V_ACTIVE(y) ((y)<<16) 266 #define CFG_H_ACTIVE(x) (x) 267 268 /* Screen H&V Porch Register */ 269 #define LCD_SPU_H_PORCH 0x011C 270 #define CFG_H_BACK_PORCH(b) ((b)<<16) 271 #define CFG_H_FRONT_PORCH(f) (f) 272 #define LCD_SPU_V_PORCH 0x0120 273 #define CFG_V_BACK_PORCH(b) ((b)<<16) 274 #define CFG_V_FRONT_PORCH(f) (f) 275 276 /* Screen Blank Color Register */ 277 #define LCD_SPU_BLANKCOLOR 0x0124 278 #define CFG_BLANKCOLOR_MASK 0x00FFFFFF 279 #define CFG_BLANKCOLOR_R_MASK 0x000000FF 280 #define CFG_BLANKCOLOR_G_MASK 0x0000FF00 281 #define CFG_BLANKCOLOR_B_MASK 0x00FF0000 282 283 /* HW Cursor Color 1&2 Register */ 284 #define LCD_SPU_ALPHA_COLOR1 0x0128 285 #define CFG_HWC_COLOR1 0x00FFFFFF 286 #define CFG_HWC_COLOR1_R(red) ((red)<<16) 287 #define CFG_HWC_COLOR1_G(green) ((green)<<8) 288 #define CFG_HWC_COLOR1_B(blue) (blue) 289 #define CFG_HWC_COLOR1_R_MASK 0x000000FF 290 #define CFG_HWC_COLOR1_G_MASK 0x0000FF00 291 #define CFG_HWC_COLOR1_B_MASK 0x00FF0000 292 #define LCD_SPU_ALPHA_COLOR2 0x012C 293 #define CFG_HWC_COLOR2 0x00FFFFFF 294 #define CFG_HWC_COLOR2_R_MASK 0x000000FF 295 #define CFG_HWC_COLOR2_G_MASK 0x0000FF00 296 #define CFG_HWC_COLOR2_B_MASK 0x00FF0000 297 298 /* Video YUV Color Key Control */ 299 #define LCD_SPU_COLORKEY_Y 0x0130 300 #define CFG_CKEY_Y2(y2) ((y2)<<24) 301 #define CFG_CKEY_Y2_MASK 0xFF000000 302 #define CFG_CKEY_Y1(y1) ((y1)<<16) 303 #define CFG_CKEY_Y1_MASK 0x00FF0000 304 #define CFG_CKEY_Y(y) ((y)<<8) 305 #define CFG_CKEY_Y_MASK 0x0000FF00 306 #define CFG_ALPHA_Y(y) (y) 307 #define CFG_ALPHA_Y_MASK 0x000000FF 308 #define LCD_SPU_COLORKEY_U 0x0134 309 #define CFG_CKEY_U2(u2) ((u2)<<24) 310 #define CFG_CKEY_U2_MASK 0xFF000000 311 #define CFG_CKEY_U1(u1) ((u1)<<16) 312 #define CFG_CKEY_U1_MASK 0x00FF0000 313 #define CFG_CKEY_U(u) ((u)<<8) 314 #define CFG_CKEY_U_MASK 0x0000FF00 315 #define CFG_ALPHA_U(u) (u) 316 #define CFG_ALPHA_U_MASK 0x000000FF 317 #define LCD_SPU_COLORKEY_V 0x0138 318 #define CFG_CKEY_V2(v2) ((v2)<<24) 319 #define CFG_CKEY_V2_MASK 0xFF000000 320 #define CFG_CKEY_V1(v1) ((v1)<<16) 321 #define CFG_CKEY_V1_MASK 0x00FF0000 322 #define CFG_CKEY_V(v) ((v)<<8) 323 #define CFG_CKEY_V_MASK 0x0000FF00 324 #define CFG_ALPHA_V(v) (v) 325 #define CFG_ALPHA_V_MASK 0x000000FF 326 327 /* Graphics/Video DMA color key enable bits in LCD_TV_CTRL1 */ 328 #define CFG_CKEY_GRA 0x2 329 #define CFG_CKEY_DMA 0x1 330 331 /* Interlace mode enable bits in LCD_TV_CTRL1 */ 332 #define CFG_TV_INTERLACE_EN (1 << 22) 333 #define CFG_TV_NIB (1 << 0) 334 335 #define LCD_PN_SEPXLCNT 0x013c /* MMP2 */ 336 337 /* SPI Read Data Register */ 338 #define LCD_SPU_SPI_RXDATA 0x0140 339 340 /* Smart Panel Read Data Register */ 341 #define LCD_SPU_ISA_RSDATA 0x0144 342 #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF 343 #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00 344 #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000 345 #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000 346 #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF 347 348 #define LCD_SPU_DBG_ISA (0x0148) /* TTC */ 349 #define LCD_SPU_DMAVLD_YC (0x014C) 350 #define LCD_SPU_DMAVLD_UV (0x0150) 351 #define LCD_SPU_DMAVLD_UVSPU_GRAVLD (0x0154) 352 353 #define LCD_READ_IOPAD (0x0148) /* MMP2*/ 354 #define LCD_DMAVLD_YC (0x014C) 355 #define LCD_DMAVLD_UV (0x0150) 356 #define LCD_TVGGRAVLD_HLEN (0x0154) 357 358 /* HWC SRAM Read Data Register */ 359 #define LCD_SPU_HWC_RDDAT 0x0158 360 361 /* Gamma Table SRAM Read Data Register */ 362 #define LCD_SPU_GAMMA_RDDAT 0x015c 363 #define CFG_GAMMA_RDDAT_MASK 0x000000FF 364 365 /* Palette Table SRAM Read Data Register */ 366 #define LCD_SPU_PALETTE_RDDAT 0x0160 367 #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF 368 369 #define LCD_SPU_DBG_DMATOP (0x0164) /* TTC */ 370 #define LCD_SPU_DBG_GRATOP (0x0168) 371 #define LCD_SPU_DBG_TXCTRL (0x016C) 372 #define LCD_SPU_DBG_SLVTOP (0x0170) 373 #define LCD_SPU_DBG_MUXTOP (0x0174) 374 375 #define LCD_SLV_DBG (0x0164) /* MMP2 */ 376 #define LCD_TVDVLD_YC (0x0168) 377 #define LCD_TVDVLD_UV (0x016C) 378 #define LCD_TVC_RDDAT (0x0170) 379 #define LCD_TV_GAMMA_RDDAT (0x0174) 380 381 /* I/O Pads Input Read Only Register */ 382 #define LCD_SPU_IOPAD_IN 0x0178 383 #define CFG_IOPAD_IN_MASK 0x0FFFFFFF 384 385 #define LCD_TV_PALETTE_RDDAT (0x0178) /* MMP2 */ 386 387 /* Reserved Read Only Registers */ 388 #define LCD_CFG_RDREG5F 0x017C 389 #define IRE_FRAME_CNT_MASK 0x000000C0 390 #define IPE_FRAME_CNT_MASK 0x00000030 391 #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */ 392 #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */ 393 394 #define LCD_FRAME_CNT (0x017C) /* MMP2 */ 395 396 /* SPI Control Register. */ 397 #define LCD_SPU_SPI_CTRL 0x0180 398 #define CFG_SCLKCNT(div) ((div)<<24) /* 0xFF~0x2 */ 399 #define CFG_SCLKCNT_MASK 0xFF000000 400 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ 401 #define CFG_RXBITS_MASK 0x00FF0000 402 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */ 403 #define CFG_TXBITS_MASK 0x0000FF00 404 #define CFG_CLKINV(clk) ((clk)<<7) 405 #define CFG_CLKINV_MASK 0x00000080 406 #define CFG_KEEPXFER(transfer) ((transfer)<<6) 407 #define CFG_KEEPXFER_MASK 0x00000040 408 #define CFG_RXBITSTO0(rx) ((rx)<<5) 409 #define CFG_RXBITSTO0_MASK 0x00000020 410 #define CFG_TXBITSTO0(tx) ((tx)<<4) 411 #define CFG_TXBITSTO0_MASK 0x00000010 412 #define CFG_SPI_ENA(spi) ((spi)<<3) 413 #define CFG_SPI_ENA_MASK 0x00000008 414 #define CFG_SPI_SEL(spi) ((spi)<<2) 415 #define CFG_SPI_SEL_MASK 0x00000004 416 #define CFG_SPI_3W4WB(wire) ((wire)<<1) 417 #define CFG_SPI_3W4WB_MASK 0x00000002 418 #define CFG_SPI_START(start) (start) 419 #define CFG_SPI_START_MASK 0x00000001 420 421 /* SPI Tx Data Register */ 422 #define LCD_SPU_SPI_TXDATA 0x0184 423 424 /* 425 1. Smart Pannel 8-bit Bus Control Register. 426 2. AHB Slave Path Data Port Register 427 */ 428 #define LCD_SPU_SMPN_CTRL 0x0188 429 430 /* DMA Control 0 Register */ 431 #define LCD_SPU_DMA_CTRL0 0x0190 432 #define CFG_NOBLENDING(nb) ((nb)<<31) 433 #define CFG_NOBLENDING_MASK 0x80000000 434 #define CFG_GAMMA_ENA(gn) ((gn)<<30) 435 #define CFG_GAMMA_ENA_MASK 0x40000000 436 #define CFG_CBSH_ENA(cn) ((cn)<<29) 437 #define CFG_CBSH_ENA_MASK 0x20000000 438 #define CFG_PALETTE_ENA(pn) ((pn)<<28) 439 #define CFG_PALETTE_ENA_MASK 0x10000000 440 #define CFG_ARBFAST_ENA(an) ((an)<<27) 441 #define CFG_ARBFAST_ENA_MASK 0x08000000 442 #define CFG_HWC_1BITMOD(mode) ((mode)<<26) 443 #define CFG_HWC_1BITMOD_MASK 0x04000000 444 #define CFG_HWC_1BITENA(mn) ((mn)<<25) 445 #define CFG_HWC_1BITENA_MASK 0x02000000 446 #define CFG_HWC_ENA(cn) ((cn)<<24) 447 #define CFG_HWC_ENA_MASK 0x01000000 448 #define CFG_DMAFORMAT(dmaformat) ((dmaformat)<<20) 449 #define CFG_DMAFORMAT_MASK 0x00F00000 450 #define CFG_GRAFORMAT(graformat) ((graformat)<<16) 451 #define CFG_GRAFORMAT_MASK 0x000F0000 452 /* for graphic part */ 453 #define CFG_GRA_FTOGGLE(toggle) ((toggle)<<15) 454 #define CFG_GRA_FTOGGLE_MASK 0x00008000 455 #define CFG_GRA_HSMOOTH(smooth) ((smooth)<<14) 456 #define CFG_GRA_HSMOOTH_MASK 0x00004000 457 #define CFG_GRA_TSTMODE(test) ((test)<<13) 458 #define CFG_GRA_TSTMODE_MASK 0x00002000 459 #define CFG_GRA_SWAPRB(swap) ((swap)<<12) 460 #define CFG_GRA_SWAPRB_MASK 0x00001000 461 #define CFG_GRA_SWAPUV(swap) ((swap)<<11) 462 #define CFG_GRA_SWAPUV_MASK 0x00000800 463 #define CFG_GRA_SWAPYU(swap) ((swap)<<10) 464 #define CFG_GRA_SWAPYU_MASK 0x00000400 465 #define CFG_GRA_SWAP_MASK 0x00001C00 466 #define CFG_YUV2RGB_GRA(cvrt) ((cvrt)<<9) 467 #define CFG_YUV2RGB_GRA_MASK 0x00000200 468 #define CFG_GRA_ENA(gra) ((gra)<<8) 469 #define CFG_GRA_ENA_MASK 0x00000100 470 #define dma0_gfx_masks (CFG_GRAFORMAT_MASK | CFG_GRA_FTOGGLE_MASK | \ 471 CFG_GRA_HSMOOTH_MASK | CFG_GRA_TSTMODE_MASK | CFG_GRA_SWAP_MASK | \ 472 CFG_YUV2RGB_GRA_MASK | CFG_GRA_ENA_MASK) 473 /* for video part */ 474 #define CFG_DMA_FTOGGLE(toggle) ((toggle)<<7) 475 #define CFG_DMA_FTOGGLE_MASK 0x00000080 476 #define CFG_DMA_HSMOOTH(smooth) ((smooth)<<6) 477 #define CFG_DMA_HSMOOTH_MASK 0x00000040 478 #define CFG_DMA_TSTMODE(test) ((test)<<5) 479 #define CFG_DMA_TSTMODE_MASK 0x00000020 480 #define CFG_DMA_SWAPRB(swap) ((swap)<<4) 481 #define CFG_DMA_SWAPRB_MASK 0x00000010 482 #define CFG_DMA_SWAPUV(swap) ((swap)<<3) 483 #define CFG_DMA_SWAPUV_MASK 0x00000008 484 #define CFG_DMA_SWAPYU(swap) ((swap)<<2) 485 #define CFG_DMA_SWAPYU_MASK 0x00000004 486 #define CFG_DMA_SWAP_MASK 0x0000001C 487 #define CFG_YUV2RGB_DMA(cvrt) ((cvrt)<<1) 488 #define CFG_YUV2RGB_DMA_MASK 0x00000002 489 #define CFG_DMA_ENA(video) (video) 490 #define CFG_DMA_ENA_MASK 0x00000001 491 #define dma0_vid_masks (CFG_DMAFORMAT_MASK | CFG_DMA_FTOGGLE_MASK | \ 492 CFG_DMA_HSMOOTH_MASK | CFG_DMA_TSTMODE_MASK | CFG_DMA_SWAP_MASK | \ 493 CFG_YUV2RGB_DMA_MASK | CFG_DMA_ENA_MASK) 494 #define dma_palette(val) ((val ? 1 : 0) << 28) 495 #define dma_fmt(vid, val) ((val & 0xf) << ((vid) ? 20 : 16)) 496 #define dma_swaprb(vid, val) ((val ? 1 : 0) << ((vid) ? 4 : 12)) 497 #define dma_swapuv(vid, val) ((val ? 1 : 0) << ((vid) ? 3 : 11)) 498 #define dma_swapyuv(vid, val) ((val ? 1 : 0) << ((vid) ? 2 : 10)) 499 #define dma_csc(vid, val) ((val ? 1 : 0) << ((vid) ? 1 : 9)) 500 #define dma_hsmooth(vid, val) ((val ? 1 : 0) << ((vid) ? 6 : 14)) 501 #define dma_mask(vid) (dma_palette(1) | dma_fmt(vid, 0xf) | dma_csc(vid, 1) \ 502 | dma_swaprb(vid, 1) | dma_swapuv(vid, 1) | dma_swapyuv(vid, 1)) 503 504 /* DMA Control 1 Register */ 505 #define LCD_SPU_DMA_CTRL1 0x0194 506 #define CFG_FRAME_TRIG(trig) ((trig)<<31) 507 #define CFG_FRAME_TRIG_MASK 0x80000000 508 #define CFG_VSYNC_TRIG(trig) ((trig)<<28) 509 #define CFG_VSYNC_TRIG_MASK 0x70000000 510 #define CFG_VSYNC_INV(inv) ((inv)<<27) 511 #define CFG_VSYNC_INV_MASK 0x08000000 512 #define CFG_COLOR_KEY_MODE(cmode) ((cmode)<<24) 513 #define CFG_COLOR_KEY_MASK 0x07000000 514 #define CFG_CARRY(carry) ((carry)<<23) 515 #define CFG_CARRY_MASK 0x00800000 516 #define CFG_LNBUF_ENA(lnbuf) ((lnbuf)<<22) 517 #define CFG_LNBUF_ENA_MASK 0x00400000 518 #define CFG_GATED_ENA(gated) ((gated)<<21) 519 #define CFG_GATED_ENA_MASK 0x00200000 520 #define CFG_PWRDN_ENA(power) ((power)<<20) 521 #define CFG_PWRDN_ENA_MASK 0x00100000 522 #define CFG_DSCALE(dscale) ((dscale)<<18) 523 #define CFG_DSCALE_MASK 0x000C0000 524 #define CFG_ALPHA_MODE(amode) ((amode)<<16) 525 #define CFG_ALPHA_MODE_MASK 0x00030000 526 #define CFG_ALPHA(alpha) ((alpha)<<8) 527 #define CFG_ALPHA_MASK 0x0000FF00 528 #define CFG_PXLCMD(pxlcmd) (pxlcmd) 529 #define CFG_PXLCMD_MASK 0x000000FF 530 531 /* SRAM Control Register */ 532 #define LCD_SPU_SRAM_CTRL 0x0198 533 #define CFG_SRAM_INIT_WR_RD(mode) ((mode)<<14) 534 #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000 535 #define CFG_SRAM_ADDR_LCDID(id) ((id)<<8) 536 #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00 537 #define CFG_SRAM_ADDR(addr) (addr) 538 #define CFG_SRAM_ADDR_MASK 0x000000FF 539 540 /* SRAM Write Data Register */ 541 #define LCD_SPU_SRAM_WRDAT 0x019C 542 543 /* SRAM RTC/WTC Control Register */ 544 #define LCD_SPU_SRAM_PARA0 0x01A0 545 546 /* SRAM Power Down Control Register */ 547 #define LCD_SPU_SRAM_PARA1 0x01A4 548 #define CFG_CSB_256x32(hwc) ((hwc)<<15) /* HWC */ 549 #define CFG_CSB_256x32_MASK 0x00008000 550 #define CFG_CSB_256x24(palette) ((palette)<<14) /* Palette */ 551 #define CFG_CSB_256x24_MASK 0x00004000 552 #define CFG_CSB_256x8(gamma) ((gamma)<<13) /* Gamma */ 553 #define CFG_CSB_256x8_MASK 0x00002000 554 #define CFG_PDWN256x32(pdwn) ((pdwn)<<7) /* HWC */ 555 #define CFG_PDWN256x32_MASK 0x00000080 556 #define CFG_PDWN256x24(pdwn) ((pdwn)<<6) /* Palette */ 557 #define CFG_PDWN256x24_MASK 0x00000040 558 #define CFG_PDWN256x8(pdwn) ((pdwn)<<5) /* Gamma */ 559 #define CFG_PDWN256x8_MASK 0x00000020 560 #define CFG_PDWN32x32(pdwn) ((pdwn)<<3) 561 #define CFG_PDWN32x32_MASK 0x00000008 562 #define CFG_PDWN16x66(pdwn) ((pdwn)<<2) 563 #define CFG_PDWN16x66_MASK 0x00000004 564 #define CFG_PDWN32x66(pdwn) ((pdwn)<<1) 565 #define CFG_PDWN32x66_MASK 0x00000002 566 #define CFG_PDWN64x66(pdwn) (pdwn) 567 #define CFG_PDWN64x66_MASK 0x00000001 568 569 /* Smart or Dumb Panel Clock Divider */ 570 #define LCD_CFG_SCLK_DIV 0x01A8 571 #define SCLK_SRC_SEL(src) ((src)<<31) 572 #define SCLK_SRC_SEL_MASK 0x80000000 573 #define SCLK_DISABLE (1<<28) 574 #define CLK_FRACDIV(frac) ((frac)<<16) 575 #define CLK_FRACDIV_MASK 0x0FFF0000 576 #define DSI1_BITCLK_DIV(div) (div<<8) 577 #define DSI1_BITCLK_DIV_MASK 0x00000F00 578 #define CLK_INT_DIV(div) (div) 579 #define CLK_INT_DIV_MASK 0x000000FF 580 581 /* Video Contrast Register */ 582 #define LCD_SPU_CONTRAST 0x01AC 583 #define CFG_BRIGHTNESS(bright) ((bright)<<16) 584 #define CFG_BRIGHTNESS_MASK 0xFFFF0000 585 #define CFG_CONTRAST(contrast) (contrast) 586 #define CFG_CONTRAST_MASK 0x0000FFFF 587 588 /* Video Saturation Register */ 589 #define LCD_SPU_SATURATION 0x01B0 590 #define CFG_C_MULTS(mult) ((mult)<<16) 591 #define CFG_C_MULTS_MASK 0xFFFF0000 592 #define CFG_SATURATION(sat) (sat) 593 #define CFG_SATURATION_MASK 0x0000FFFF 594 595 /* Video Hue Adjust Register */ 596 #define LCD_SPU_CBSH_HUE 0x01B4 597 #define CFG_SIN0(sin0) ((sin0)<<16) 598 #define CFG_SIN0_MASK 0xFFFF0000 599 #define CFG_COS0(con0) (con0) 600 #define CFG_COS0_MASK 0x0000FFFF 601 602 /* Dump LCD Panel Control Register */ 603 #define LCD_SPU_DUMB_CTRL 0x01B8 604 #define CFG_DUMBMODE(mode) ((mode)<<28) 605 #define CFG_DUMBMODE_MASK 0xF0000000 606 #define CFG_INTFRBSWAP(mode) ((mode)<<24) 607 #define CFG_INTFRBSWAP_MASK 0x0F000000 608 #define CFG_LCDGPIO_O(data) ((data)<<20) 609 #define CFG_LCDGPIO_O_MASK 0x0FF00000 610 #define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12) 611 #define CFG_LCDGPIO_ENA_MASK 0x000FF000 612 #define CFG_BIAS_OUT(bias) ((bias)<<8) 613 #define CFG_BIAS_OUT_MASK 0x00000100 614 #define CFG_REVERSE_RGB(RGB) ((RGB)<<7) 615 #define CFG_REVERSE_RGB_MASK 0x00000080 616 #define CFG_INV_COMPBLANK(blank) ((blank)<<6) 617 #define CFG_INV_COMPBLANK_MASK 0x00000040 618 #define CFG_INV_COMPSYNC(sync) ((sync)<<5) 619 #define CFG_INV_COMPSYNC_MASK 0x00000020 620 #define CFG_INV_HENA(hena) ((hena)<<4) 621 #define CFG_INV_HENA_MASK 0x00000010 622 #define CFG_INV_VSYNC(vsync) ((vsync)<<3) 623 #define CFG_INV_VSYNC_MASK 0x00000008 624 #define CFG_INV_HSYNC(hsync) ((hsync)<<2) 625 #define CFG_INV_HSYNC_MASK 0x00000004 626 #define CFG_INV_PCLK(pclk) ((pclk)<<1) 627 #define CFG_INV_PCLK_MASK 0x00000002 628 #define CFG_DUMB_ENA(dumb) (dumb) 629 #define CFG_DUMB_ENA_MASK 0x00000001 630 631 /* LCD I/O Pads Control Register */ 632 #define SPU_IOPAD_CONTROL 0x01BC 633 #define CFG_GRA_VM_ENA(vm) ((vm)<<15) 634 #define CFG_GRA_VM_ENA_MASK 0x00008000 635 #define CFG_DMA_VM_ENA(vm) ((vm)<<13) 636 #define CFG_DMA_VM_ENA_MASK 0x00002000 637 #define CFG_CMD_VM_ENA(vm) ((vm)<<12) 638 #define CFG_CMD_VM_ENA_MASK 0x00001000 639 #define CFG_CSC(csc) ((csc)<<8) 640 #define CFG_CSC_MASK 0x00000300 641 #define CFG_BOUNDARY(size) ((size)<<5) 642 #define CFG_BOUNDARY_MASK 0x00000020 643 #define CFG_BURST(len) ((len)<<4) 644 #define CFG_BURST_MASK 0x00000010 645 #define CFG_IOPADMODE(iopad) (iopad) 646 #define CFG_IOPADMODE_MASK 0x0000000F 647 648 /* LCD Interrupt Control Register */ 649 #define SPU_IRQ_ENA 0x01C0 650 #define DMA_FRAME_IRQ0_ENA(irq) ((irq)<<31) 651 #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000 652 #define DMA_FRAME_IRQ1_ENA(irq) ((irq)<<30) 653 #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000 654 #define DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<29) 655 #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000 656 #define AXI_BUS_ERROR_IRQ_ENA(irq) ((irq)<<28) 657 #define AXI_BUS_ERROR_IRQ_ENA_MASK 0x10000000 658 #define GRA_FRAME_IRQ0_ENA(irq) ((irq)<<27) 659 #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000 660 #define GRA_FRAME_IRQ1_ENA(irq) ((irq)<<26) 661 #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000 662 #define GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<25) 663 #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000 664 #define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq)<<23) 665 #define VSYNC_IRQ_ENA_MASK 0x00800000 666 #define DUMB_FRAMEDONE_ENA(fdone) ((fdone)<<22) 667 #define DUMB_FRAMEDONE_ENA_MASK 0x00400000 668 #define TWC_FRAMEDONE_ENA(fdone) ((fdone)<<21) 669 #define TWC_FRAMEDONE_ENA_MASK 0x00200000 670 #define HWC_FRAMEDONE_ENA(fdone) ((fdone)<<20) 671 #define HWC_FRAMEDONE_ENA_MASK 0x00100000 672 #define SLV_IRQ_ENA(irq) ((irq)<<19) 673 #define SLV_IRQ_ENA_MASK 0x00080000 674 #define SPI_IRQ_ENA(irq) ((irq)<<18) 675 #define SPI_IRQ_ENA_MASK 0x00040000 676 #define PWRDN_IRQ_ENA(irq) ((irq)<<17) 677 #define PWRDN_IRQ_ENA_MASK 0x00020000 678 #define AXI_LATENCY_TOO_LONG_IRQ_ENA(irq) ((irq)<<16) 679 #define AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK 0x00010000 680 #define CLEAN_SPU_IRQ_ISR(irq) (irq) 681 #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF 682 #define TV_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<15) 683 #define TV_DMA_FRAME_IRQ0_ENA_MASK 0x00008000 684 #define TV_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<14) 685 #define TV_DMA_FRAME_IRQ1_ENA_MASK 0x00004000 686 #define TV_DMA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<13) 687 #define TV_DMA_FF_UNDERFLOW_ENA_MASK 0x00002000 688 #define TVSYNC_IRQ_ENA(irq) ((irq)<<12) 689 #define TVSYNC_IRQ_ENA_MASK 0x00001000 690 #define TV_FRAME_IRQ0_ENA(irq) ((irq)<<11) 691 #define TV_FRAME_IRQ0_ENA_MASK 0x00000800 692 #define TV_FRAME_IRQ1_ENA(irq) ((irq)<<10) 693 #define TV_FRAME_IRQ1_ENA_MASK 0x00000400 694 #define TV_GRA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<9) 695 #define TV_GRA_FF_UNDERFLOW_ENA_MASK 0x00000200 696 #define TV_FRAMEDONE_ENA(irq) ((irq)<<8) 697 #define TV_FRAMEDONE_ENA_MASK 0x00000100 698 699 /* FIXME - JUST GUESS */ 700 #define PN2_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<7) 701 #define PN2_DMA_FRAME_IRQ0_ENA_MASK 0x00000080 702 #define PN2_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<6) 703 #define PN2_DMA_FRAME_IRQ1_ENA_MASK 0x00000040 704 #define PN2_DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<5) 705 #define PN2_DMA_FF_UNDERFLOW_ENA_MASK 0x00000020 706 #define PN2_GRA_FRAME_IRQ0_ENA(irq) ((irq)<<3) 707 #define PN2_GRA_FRAME_IRQ0_ENA_MASK 0x00000008 708 #define PN2_GRA_FRAME_IRQ1_ENA(irq) ((irq)<<2) 709 #define PN2_GRA_FRAME_IRQ1_ENA_MASK 0x04000004 710 #define PN2_GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<1) 711 #define PN2_GRA_FF_UNDERFLOW_ENA_MASK 0x00000002 712 #define PN2_VSYNC_IRQ_ENA(irq) ((irq)<<0) 713 #define PN2_SYNC_IRQ_ENA_MASK 0x00000001 714 715 #define gf0_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ0_ENA_MASK \ 716 : PN2_GRA_FRAME_IRQ0_ENA_MASK) : GRA_FRAME_IRQ0_ENA_MASK) 717 #define gf1_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ1_ENA_MASK \ 718 : PN2_GRA_FRAME_IRQ1_ENA_MASK) : GRA_FRAME_IRQ1_ENA_MASK) 719 #define vsync_imask(id) ((id) ? (((id) & 1) ? TVSYNC_IRQ_ENA_MASK \ 720 : PN2_SYNC_IRQ_ENA_MASK) : VSYNC_IRQ_ENA_MASK) 721 #define vsync_imasks (vsync_imask(0) | vsync_imask(1)) 722 723 #define display_done_imask(id) ((id) ? (((id) & 1) ? TV_FRAMEDONE_ENA_MASK\ 724 : (PN2_DMA_FRAME_IRQ0_ENA_MASK | PN2_DMA_FRAME_IRQ1_ENA_MASK))\ 725 : DUMB_FRAMEDONE_ENA_MASK) 726 727 #define display_done_imasks (display_done_imask(0) | display_done_imask(1)) 728 729 #define vf0_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ0_ENA_MASK \ 730 : PN2_DMA_FRAME_IRQ0_ENA_MASK) : DMA_FRAME_IRQ0_ENA_MASK) 731 #define vf1_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ1_ENA_MASK \ 732 : PN2_DMA_FRAME_IRQ1_ENA_MASK) : DMA_FRAME_IRQ1_ENA_MASK) 733 734 #define gfx_imasks (gf0_imask(0) | gf1_imask(0) | gf0_imask(1) | \ 735 gf1_imask(1)) 736 #define vid_imasks (vf0_imask(0) | vf1_imask(0) | vf0_imask(1) | \ 737 vf1_imask(1)) 738 #define vid_imask(id) (display_done_imask(id)) 739 740 #define pn1_imasks (gf0_imask(0) | gf1_imask(0) | vsync_imask(0) | \ 741 display_done_imask(0) | vf0_imask(0) | vf1_imask(0)) 742 #define tv_imasks (gf0_imask(1) | gf1_imask(1) | vsync_imask(1) | \ 743 display_done_imask(1) | vf0_imask(1) | vf1_imask(1)) 744 #define path_imasks(id) ((id) ? (tv_imasks) : (pn1_imasks)) 745 746 /* error indications */ 747 #define vid_udflow_imask(id) ((id) ? (((id) & 1) ? \ 748 (TV_DMA_FF_UNDERFLOW_ENA_MASK) : (PN2_DMA_FF_UNDERFLOW_ENA_MASK)) : \ 749 (DMA_FF_UNDERFLOW_ENA_MASK)) 750 #define gfx_udflow_imask(id) ((id) ? (((id) & 1) ? \ 751 (TV_GRA_FF_UNDERFLOW_ENA_MASK) : (PN2_GRA_FF_UNDERFLOW_ENA_MASK)) : \ 752 (GRA_FF_UNDERFLOW_ENA_MASK)) 753 754 #define err_imask(id) (vid_udflow_imask(id) | gfx_udflow_imask(id) | \ 755 AXI_BUS_ERROR_IRQ_ENA_MASK | AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK) 756 #define err_imasks (err_imask(0) | err_imask(1) | err_imask(2)) 757 /* LCD Interrupt Status Register */ 758 #define SPU_IRQ_ISR 0x01C4 759 #define DMA_FRAME_IRQ0(irq) ((irq)<<31) 760 #define DMA_FRAME_IRQ0_MASK 0x80000000 761 #define DMA_FRAME_IRQ1(irq) ((irq)<<30) 762 #define DMA_FRAME_IRQ1_MASK 0x40000000 763 #define DMA_FF_UNDERFLOW(ff) ((ff)<<29) 764 #define DMA_FF_UNDERFLOW_MASK 0x20000000 765 #define AXI_BUS_ERROR_IRQ(irq) ((irq)<<28) 766 #define AXI_BUS_ERROR_IRQ_MASK 0x10000000 767 #define GRA_FRAME_IRQ0(irq) ((irq)<<27) 768 #define GRA_FRAME_IRQ0_MASK 0x08000000 769 #define GRA_FRAME_IRQ1(irq) ((irq)<<26) 770 #define GRA_FRAME_IRQ1_MASK 0x04000000 771 #define GRA_FF_UNDERFLOW(ff) ((ff)<<25) 772 #define GRA_FF_UNDERFLOW_MASK 0x02000000 773 #define VSYNC_IRQ(vsync_irq) ((vsync_irq)<<23) 774 #define VSYNC_IRQ_MASK 0x00800000 775 #define DUMB_FRAMEDONE(fdone) ((fdone)<<22) 776 #define DUMB_FRAMEDONE_MASK 0x00400000 777 #define TWC_FRAMEDONE(fdone) ((fdone)<<21) 778 #define TWC_FRAMEDONE_MASK 0x00200000 779 #define HWC_FRAMEDONE(fdone) ((fdone)<<20) 780 #define HWC_FRAMEDONE_MASK 0x00100000 781 #define SLV_IRQ(irq) ((irq)<<19) 782 #define SLV_IRQ_MASK 0x00080000 783 #define SPI_IRQ(irq) ((irq)<<18) 784 #define SPI_IRQ_MASK 0x00040000 785 #define PWRDN_IRQ(irq) ((irq)<<17) 786 #define PWRDN_IRQ_MASK 0x00020000 787 #define AXI_LATENCY_TOO_LONGR_IRQ(irq) ((irq)<<16) 788 #define AXI_LATENCY_TOO_LONGR_IRQ_MASK 0x00010000 789 #define TV_DMA_FRAME_IRQ0(irq) ((irq)<<15) 790 #define TV_DMA_FRAME_IRQ0_MASK 0x00008000 791 #define TV_DMA_FRAME_IRQ1(irq) ((irq)<<14) 792 #define TV_DMA_FRAME_IRQ1_MASK 0x00004000 793 #define TV_DMA_FF_UNDERFLOW(unerrun) ((unerrun)<<13) 794 #define TV_DMA_FF_UNDERFLOW_MASK 0x00002000 795 #define TVSYNC_IRQ(irq) ((irq)<<12) 796 #define TVSYNC_IRQ_MASK 0x00001000 797 #define TV_FRAME_IRQ0(irq) ((irq)<<11) 798 #define TV_FRAME_IRQ0_MASK 0x00000800 799 #define TV_FRAME_IRQ1(irq) ((irq)<<10) 800 #define TV_FRAME_IRQ1_MASK 0x00000400 801 #define TV_GRA_FF_UNDERFLOW(unerrun) ((unerrun)<<9) 802 #define TV_GRA_FF_UNDERFLOW_MASK 0x00000200 803 #define PN2_DMA_FRAME_IRQ0(irq) ((irq)<<7) 804 #define PN2_DMA_FRAME_IRQ0_MASK 0x00000080 805 #define PN2_DMA_FRAME_IRQ1(irq) ((irq)<<6) 806 #define PN2_DMA_FRAME_IRQ1_MASK 0x00000040 807 #define PN2_DMA_FF_UNDERFLOW(ff) ((ff)<<5) 808 #define PN2_DMA_FF_UNDERFLOW_MASK 0x00000020 809 #define PN2_GRA_FRAME_IRQ0(irq) ((irq)<<3) 810 #define PN2_GRA_FRAME_IRQ0_MASK 0x00000008 811 #define PN2_GRA_FRAME_IRQ1(irq) ((irq)<<2) 812 #define PN2_GRA_FRAME_IRQ1_MASK 0x04000004 813 #define PN2_GRA_FF_UNDERFLOW(ff) ((ff)<<1) 814 #define PN2_GRA_FF_UNDERFLOW_MASK 0x00000002 815 #define PN2_VSYNC_IRQ(irq) ((irq)<<0) 816 #define PN2_SYNC_IRQ_MASK 0x00000001 817 818 /* LCD FIFO Depth register */ 819 #define LCD_FIFO_DEPTH 0x01c8 820 #define VIDEO_FIFO(fi) ((fi) << 0) 821 #define VIDEO_FIFO_MASK 0x00000003 822 #define GRAPHIC_FIFO(fi) ((fi) << 2) 823 #define GRAPHIC_FIFO_MASK 0x0000000c 824 825 /* read-only */ 826 #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000 827 #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000 828 #define DMA_FRAME_CNT_ISR_MASK 0x00003000 829 #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800 830 #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400 831 #define GRA_FRAME_CNT_ISR_MASK 0x00000300 832 #define VSYNC_IRQ_LEVEL_MASK 0x00000080 833 #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040 834 #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020 835 #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010 836 #define SLV_FF_EMPTY_MASK 0x00000008 837 #define DMA_FF_ALLEMPTY_MASK 0x00000004 838 #define GRA_FF_ALLEMPTY_MASK 0x00000002 839 #define PWRDN_IRQ_LEVEL_MASK 0x00000001 840 841 /* 32 bit LCD Interrupt Reset Status*/ 842 #define SPU_IRQ_RSR (0x01C8) 843 /* 32 bit Panel Path Graphic Partial Display Horizontal Control Register*/ 844 #define LCD_GRA_CUTHPXL (0x01CC) 845 /* 32 bit Panel Path Graphic Partial Display Vertical Control Register*/ 846 #define LCD_GRA_CUTVLN (0x01D0) 847 /* 32 bit TV Path Graphic Partial Display Horizontal Control Register*/ 848 #define LCD_TVG_CUTHPXL (0x01D4) 849 /* 32 bit TV Path Graphic Partial Display Vertical Control Register*/ 850 #define LCD_TVG_CUTVLN (0x01D8) 851 /* 32 bit LCD Global Control Register*/ 852 #define LCD_TOP_CTRL (0x01DC) 853 /* 32 bit LCD SQU Line Buffer Control Register 1*/ 854 #define LCD_SQULN1_CTRL (0x01E0) 855 /* 32 bit LCD SQU Line Buffer Control Register 2*/ 856 #define LCD_SQULN2_CTRL (0x01E4) 857 #define squln_ctrl(id) ((id) ? (((id) & 1) ? LCD_SQULN2_CTRL : \ 858 LCD_PN2_SQULN1_CTRL) : LCD_SQULN1_CTRL) 859 860 /* 32 bit LCD Mixed Overlay Control Register */ 861 #define LCD_AFA_ALL2ONE (0x01E8) 862 863 #define LCD_PN2_SCLK_DIV (0x01EC) 864 #define LCD_PN2_TCLK_DIV (0x01F0) 865 #define LCD_LVDS_SCLK_DIV_WR (0x01F4) 866 #define LCD_LVDS_SCLK_DIV_RD (0x01FC) 867 #define PN2_LCD_DMA_START_ADDR_Y0 (0x0200) 868 #define PN2_LCD_DMA_START_ADDR_U0 (0x0204) 869 #define PN2_LCD_DMA_START_ADDR_V0 (0x0208) 870 #define PN2_LCD_DMA_START_ADDR_C0 (0x020C) 871 #define PN2_LCD_DMA_START_ADDR_Y1 (0x0210) 872 #define PN2_LCD_DMA_START_ADDR_U1 (0x0214) 873 #define PN2_LCD_DMA_START_ADDR_V1 (0x0218) 874 #define PN2_LCD_DMA_START_ADDR_C1 (0x021C) 875 #define PN2_LCD_DMA_PITCH_YC (0x0220) 876 #define PN2_LCD_DMA_PITCH_UV (0x0224) 877 #define PN2_LCD_DMA_OVSA_HPXL_VLN (0x0228) 878 #define PN2_LCD_DMA_HPXL_VLN (0x022C) 879 #define PN2_LCD_DMAZM_HPXL_VLN (0x0230) 880 #define PN2_LCD_GRA_START_ADDR0 (0x0234) 881 #define PN2_LCD_GRA_START_ADDR1 (0x0238) 882 #define PN2_LCD_GRA_PITCH (0x023C) 883 #define PN2_LCD_GRA_OVSA_HPXL_VLN (0x0240) 884 #define PN2_LCD_GRA_HPXL_VLN (0x0244) 885 #define PN2_LCD_GRAZM_HPXL_VLN (0x0248) 886 #define PN2_LCD_HWC_OVSA_HPXL_VLN (0x024C) 887 #define PN2_LCD_HWC_HPXL_VLN (0x0250) 888 #define LCD_PN2_V_H_TOTAL (0x0254) 889 #define LCD_PN2_V_H_ACTIVE (0x0258) 890 #define LCD_PN2_H_PORCH (0x025C) 891 #define LCD_PN2_V_PORCH (0x0260) 892 #define LCD_PN2_BLANKCOLOR (0x0264) 893 #define LCD_PN2_ALPHA_COLOR1 (0x0268) 894 #define LCD_PN2_ALPHA_COLOR2 (0x026C) 895 #define LCD_PN2_COLORKEY_Y (0x0270) 896 #define LCD_PN2_COLORKEY_U (0x0274) 897 #define LCD_PN2_COLORKEY_V (0x0278) 898 #define LCD_PN2_SEPXLCNT (0x027C) 899 #define LCD_TV_V_H_TOTAL_FLD (0x0280) 900 #define LCD_TV_V_PORCH_FLD (0x0284) 901 #define LCD_TV_SEPXLCNT_FLD (0x0288) 902 903 #define LCD_2ND_ALPHA (0x0294) 904 #define LCD_PN2_CONTRAST (0x0298) 905 #define LCD_PN2_SATURATION (0x029c) 906 #define LCD_PN2_CBSH_HUE (0x02a0) 907 #define LCD_TIMING_EXT (0x02C0) 908 #define LCD_PN2_LAYER_ALPHA_SEL1 (0x02c4) 909 #define LCD_PN2_CTRL0 (0x02C8) 910 #define TV_LAYER_ALPHA_SEL1 (0x02cc) 911 #define LCD_SMPN2_CTRL (0x02D0) 912 #define LCD_IO_OVERL_MAP_CTRL (0x02D4) 913 #define LCD_DUMB2_CTRL (0x02d8) 914 #define LCD_PN2_CTRL1 (0x02DC) 915 #define PN2_IOPAD_CONTROL (0x02E0) 916 #define LCD_PN2_SQULN1_CTRL (0x02E4) 917 #define PN2_LCD_GRA_CUTHPXL (0x02e8) 918 #define PN2_LCD_GRA_CUTVLN (0x02ec) 919 #define LCD_PN2_SQULN2_CTRL (0x02F0) 920 #define ALL_LAYER_ALPHA_SEL (0x02F4) 921 922 #define TIMING_MASTER_CONTROL (0x02F8) 923 #define MASTER_ENH(id) (1 << (id)) 924 #define MASTER_ENV(id) (1 << ((id) + 4)) 925 926 #define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8) 927 #define timing_master_config(path, dsi_id, lcd_id) \ 928 (MASTER_ENH(path) | MASTER_ENV(path) | \ 929 (((lcd_id) + ((dsi_id) << 1)) << DSI_START_SEL_SHIFT(path))) 930 931 #define LCD_2ND_BLD_CTL (0x02Fc) 932 #define LVDS_SRC_MASK (3 << 30) 933 #define LVDS_SRC_SHIFT (30) 934 #define LVDS_FMT_MASK (1 << 28) 935 #define LVDS_FMT_SHIFT (28) 936 937 #define CLK_SCLK (1 << 0) 938 #define CLK_LVDS_RD (1 << 1) 939 #define CLK_LVDS_WR (1 << 2) 940 941 #define gra_partdisp_ctrl_hor(id) ((id) ? (((id) & 1) ? \ 942 LCD_TVG_CUTHPXL : PN2_LCD_GRA_CUTHPXL) : LCD_GRA_CUTHPXL) 943 #define gra_partdisp_ctrl_ver(id) ((id) ? (((id) & 1) ? \ 944 LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN) 945 946 /* 947 * defined for Configure Dumb Mode 948 * defined for Configure Dumb Mode 949 * DUMB LCD Panel bit[31:28] 950 */ 951 #define DUMB16_RGB565_0 0x0 952 #define DUMB16_RGB565_1 0x1 953 #define DUMB18_RGB666_0 0x2 954 #define DUMB18_RGB666_1 0x3 955 #define DUMB12_RGB444_0 0x4 956 #define DUMB12_RGB444_1 0x5 957 #define DUMB24_RGB888_0 0x6 958 #define DUMB_BLANK 0x7 959 960 /* 961 * defined for Configure I/O Pin Allocation Mode 962 * LCD LCD I/O Pads control register bit[3:0] 963 */ 964 #define IOPAD_DUMB24 0x0 965 #define IOPAD_DUMB18SPI 0x1 966 #define IOPAD_DUMB18GPIO 0x2 967 #define IOPAD_DUMB16SPI 0x3 968 #define IOPAD_DUMB16GPIO 0x4 969 #define IOPAD_DUMB12 0x5 970 #define IOPAD_SMART18SPI 0x6 971 #define IOPAD_SMART16SPI 0x7 972 #define IOPAD_SMART8BOTH 0x8 973 #define IOPAD_DUMB18_SMART8 0x9 974 #define IOPAD_DUMB16_SMART8SPI 0xa 975 #define IOPAD_DUMB16_SMART8GPIO 0xb 976 #define IOPAD_DUMB16_DUMB16 0xc 977 #define IOPAD_SMART8_SMART8 0xc 978 979 /* 980 *defined for indicating boundary and cycle burst length 981 */ 982 #define CFG_BOUNDARY_1KB (1<<5) 983 #define CFG_BOUNDARY_4KB (0<<5) 984 #define CFG_CYC_BURST_LEN16 (1<<4) 985 #define CFG_CYC_BURST_LEN8 (0<<4) 986 987 /* SRAM ID */ 988 #define SRAMID_GAMMA_YR 0x0 989 #define SRAMID_GAMMA_UG 0x1 990 #define SRAMID_GAMMA_VB 0x2 991 #define SRAMID_PALATTE 0x3 992 #define SRAMID_HWC 0xf 993 994 /* SRAM INIT Read/Write */ 995 #define SRAMID_INIT_READ 0x0 996 #define SRAMID_INIT_WRITE 0x2 997 #define SRAMID_INIT_DEFAULT 0x3 998 999 /* 1000 * defined VSYNC selection mode for DMA control 1 register 1001 * DMA1 bit[30:28] 1002 */ 1003 #define VMODE_SMPN 0x0 1004 #define VMODE_SMPNIRQ 0x1 1005 #define VMODE_DUMB 0x2 1006 #define VMODE_IPE 0x3 1007 #define VMODE_IRE 0x4 1008 1009 /* 1010 * defined Configure Alpha and Alpha mode for DMA control 1 register 1011 * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode) 1012 */ 1013 /* ALPHA mode */ 1014 #define MODE_ALPHA_DMA 0x0 1015 #define MODE_ALPHA_GRA 0x1 1016 #define MODE_ALPHA_CFG 0x2 1017 1018 /* alpha value */ 1019 #define ALPHA_NOGRAPHIC 0xFF /* all video, no graphic */ 1020 #define ALPHA_NOVIDEO 0x00 /* all graphic, no video */ 1021 #define ALPHA_GRAPHNVIDEO 0x0F /* Selects graphic & video */ 1022 1023 /* 1024 * defined Pixel Command for DMA control 1 register 1025 * DMA1 bit[07:00] 1026 */ 1027 #define PIXEL_CMD 0x81 1028 1029 /* DSI */ 1030 /* DSI1 - 4 Lane Controller base */ 1031 #define DSI1_REGS_PHYSICAL_BASE 0xD420B800 1032 /* DSI2 - 3 Lane Controller base */ 1033 #define DSI2_REGS_PHYSICAL_BASE 0xD420BA00 1034 1035 /* DSI Controller Registers */ 1036 struct dsi_lcd_regs { 1037 #define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */ 1038 #define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */ 1039 u32 ctrl0; 1040 u32 ctrl1; 1041 u32 reserved1[2]; 1042 1043 #define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */ 1044 #define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */ 1045 #define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */ 1046 #define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */ 1047 #define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */ 1048 #define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */ 1049 #define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */ 1050 u32 timing0; 1051 u32 timing1; 1052 u32 timing2; 1053 u32 timing3; 1054 u32 wc0; 1055 u32 wc1; 1056 u32 wc2; 1057 u32 reserved2[1]; 1058 u32 slot_cnt0; 1059 u32 slot_cnt1; 1060 u32 reserved3[2]; 1061 u32 status_0; 1062 u32 status_1; 1063 u32 status_2; 1064 u32 status_3; 1065 u32 status_4; 1066 }; 1067 1068 struct dsi_regs { 1069 #define DSI_CTRL_0 0x000 /* DSI control register 0 */ 1070 #define DSI_CTRL_1 0x004 /* DSI control register 1 */ 1071 u32 ctrl0; 1072 u32 ctrl1; 1073 u32 reserved1[2]; 1074 u32 irq_status; 1075 u32 irq_mask; 1076 u32 reserved2[2]; 1077 1078 #define DSI_CPU_CMD_0 0x020 /* DSI CPU packet command register 0 */ 1079 #define DSI_CPU_CMD_1 0x024 /* DSU CPU Packet Command Register 1 */ 1080 #define DSI_CPU_CMD_3 0x02C /* DSU CPU Packet Command Register 3 */ 1081 #define DSI_CPU_WDAT_0 0x030 /* DSI CUP */ 1082 u32 cmd0; 1083 u32 cmd1; 1084 u32 cmd2; 1085 u32 cmd3; 1086 u32 dat0; 1087 u32 status0; 1088 u32 status1; 1089 u32 status2; 1090 u32 status3; 1091 u32 status4; 1092 u32 reserved3[2]; 1093 1094 u32 smt_cmd; 1095 u32 smt_ctrl0; 1096 u32 smt_ctrl1; 1097 u32 reserved4[1]; 1098 1099 u32 rx0_status; 1100 1101 /* Rx Packet Header - data from slave device */ 1102 #define DSI_RX_PKT_HDR_0 0x064 1103 u32 rx0_header; 1104 u32 rx1_status; 1105 u32 rx1_header; 1106 u32 rx_ctrl; 1107 u32 rx_ctrl1; 1108 u32 rx2_status; 1109 u32 rx2_header; 1110 u32 reserved5[1]; 1111 1112 u32 phy_ctrl1; 1113 #define DSI_PHY_CTRL_2 0x088 /* DSI DPHI Control Register 2 */ 1114 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */ 1115 u32 phy_ctrl2; 1116 u32 phy_ctrl3; 1117 u32 phy_status0; 1118 u32 phy_status1; 1119 u32 reserved6[5]; 1120 u32 phy_status2; 1121 1122 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */ 1123 u32 phy_rcomp0; 1124 u32 reserved7[3]; 1125 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */ 1126 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */ 1127 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */ 1128 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */ 1129 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */ 1130 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */ 1131 u32 phy_timing0; 1132 u32 phy_timing1; 1133 u32 phy_timing2; 1134 u32 phy_timing3; 1135 u32 phy_code_0; 1136 u32 phy_code_1; 1137 u32 reserved8[2]; 1138 u32 mem_ctrl; 1139 u32 tx_timer; 1140 u32 rx_timer; 1141 u32 turn_timer; 1142 u32 reserved9[4]; 1143 1144 #define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */ 1145 #define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */ 1146 #define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */ 1147 #define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */ 1148 #define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */ 1149 #define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */ 1150 #define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */ 1151 #define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */ 1152 #define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */ 1153 struct dsi_lcd_regs lcd1; 1154 u32 reserved10[11]; 1155 struct dsi_lcd_regs lcd2; 1156 }; 1157 1158 #define DSI_LCD2_CTRL_0 0x180 /* DSI Active Panel 2 Control register 0 */ 1159 #define DSI_LCD2_CTRL_1 0x184 /* DSI Active Panel 2 Control register 1 */ 1160 #define DSI_LCD2_TIMING_0 0x190 /* Timing register 0 */ 1161 #define DSI_LCD2_TIMING_1 0x194 /* Timing register 1 */ 1162 #define DSI_LCD2_TIMING_2 0x198 /* Timing register 2 */ 1163 #define DSI_LCD2_TIMING_3 0x19C /* Timing register 3 */ 1164 #define DSI_LCD2_WC_0 0x1A0 /* Word Count register 0 */ 1165 #define DSI_LCD2_WC_1 0x1A4 /* Word Count register 1 */ 1166 #define DSI_LCD2_WC_2 0x1A8 /* Word Count register 2 */ 1167 1168 /* DSI_CTRL_0 0x0000 DSI Control Register 0 */ 1169 #define DSI_CTRL_0_CFG_SOFT_RST (1<<31) 1170 #define DSI_CTRL_0_CFG_SOFT_RST_REG (1<<30) 1171 #define DSI_CTRL_0_CFG_LCD1_TX_EN (1<<8) 1172 #define DSI_CTRL_0_CFG_LCD1_SLV (1<<4) 1173 #define DSI_CTRL_0_CFG_LCD1_EN (1<<0) 1174 1175 /* DSI_CTRL_1 0x0004 DSI Control Register 1 */ 1176 #define DSI_CTRL_1_CFG_EOTP (1<<8) 1177 #define DSI_CTRL_1_CFG_RSVD (2<<4) 1178 #define DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK (3<<2) 1179 #define DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT 2 1180 #define DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK (3<<0) 1181 #define DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT 0 1182 1183 /* DSI_LCD1_CTRL_1 0x0104 DSI Active Panel 1 Control Register 1 */ 1184 /* LCD 1 Vsync Reset Enable */ 1185 #define DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN (1<<31) 1186 /* LCD 1 2K Pixel Buffer Mode Enable */ 1187 #define DSI_LCD1_CTRL_1_CFG_L1_M2K_EN (1<<30) 1188 /* Bit(s) DSI_LCD1_CTRL_1_RSRV_29_23 reserved */ 1189 /* Long Blanking Packet Enable */ 1190 #define DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN (1<<22) 1191 /* Extra Long Blanking Packet Enable */ 1192 #define DSI_LCD1_CTRL_1_CFG_L1_HEX_PKT_EN (1<<21) 1193 /* Front Porch Packet Enable */ 1194 #define DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN (1<<20) 1195 /* hact Packet Enable */ 1196 #define DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN (1<<19) 1197 /* Back Porch Packet Enable */ 1198 #define DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN (1<<18) 1199 /* hse Packet Enable */ 1200 #define DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN (1<<17) 1201 /* hsa Packet Enable */ 1202 #define DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN (1<<16) 1203 /* All Item Enable after Pixel Data */ 1204 #define DSI_LCD1_CTRL_1_CFG_L1_ALL_SLOT_EN (1<<15) 1205 /* Extra Long Packet Enable after Pixel Data */ 1206 #define DSI_LCD1_CTRL_1_CFG_L1_HEX_SLOT_EN (1<<14) 1207 /* Bit(s) DSI_LCD1_CTRL_1_RSRV_13_11 reserved */ 1208 /* Turn Around Bus at Last h Line */ 1209 #define DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN (1<<10) 1210 /* Go to Low Power Every Frame */ 1211 #define DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN (1<<9) 1212 /* Go to Low Power Every Line */ 1213 #define DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN (1<<8) 1214 /* Bit(s) DSI_LCD1_CTRL_1_RSRV_7_4 reserved */ 1215 /* DSI Transmission Mode for LCD 1 */ 1216 #define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT 2 1217 #define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_MASK (3<<2) 1218 /* LCD 1 Input Data RGB Mode for LCD 1 */ 1219 #define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT 0 1220 #define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_MASK (3<<2) 1221 1222 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */ 1223 /* Bit(s) DSI_PHY_CTRL_2_RSRV_31_12 reserved */ 1224 /* DPHY LP Receiver Enable */ 1225 #define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_MASK (0xf<<8) 1226 #define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_SHIFT 8 1227 /* DPHY Data Lane Enable */ 1228 #define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_MASK (0xf<<4) 1229 #define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT 4 1230 /* DPHY Bus Turn Around */ 1231 #define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_MASK (0xf) 1232 #define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_SHIFT 0 1233 1234 /* DSI_CPU_CMD_1 0x0024 DSI CPU Packet Command Register 1 */ 1235 /* Bit(s) DSI_CPU_CMD_1_RSRV_31_24 reserved */ 1236 /* LPDT TX Enable */ 1237 #define DSI_CPU_CMD_1_CFG_TXLP_LPDT_MASK (0xf<<20) 1238 #define DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT 20 1239 /* ULPS TX Enable */ 1240 #define DSI_CPU_CMD_1_CFG_TXLP_ULPS_MASK (0xf<<16) 1241 #define DSI_CPU_CMD_1_CFG_TXLP_ULPS_SHIFT 16 1242 /* Low Power TX Trigger Code */ 1243 #define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_MASK (0xffff) 1244 #define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT 0 1245 1246 /* DSI_PHY_TIME_0 0x00c0 DPHY Timing Control Register 0 */ 1247 /* Length of HS Exit Period in tx_clk_esc Cycles */ 1248 #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_MASK (0xff<<24) 1249 #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT 24 1250 /* DPHY HS Trail Period Length */ 1251 #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_MASK (0xff<<16) 1252 #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT 16 1253 /* DPHY HS Zero State Length */ 1254 #define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_MASK (0xff<<8) 1255 #define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT 8 1256 /* DPHY HS Prepare State Length */ 1257 #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_MASK (0xff) 1258 #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_SHIFT 0 1259 1260 /* DSI_PHY_TIME_1 0x00c4 DPHY Timing Control Register 1 */ 1261 /* Time to Drive LP-00 by New Transmitter */ 1262 #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_MASK (0xff<<24) 1263 #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT 24 1264 /* Time to Drive LP-00 after Turn Request */ 1265 #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_MASK (0xff<<16) 1266 #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT 16 1267 /* DPHY HS Wakeup Period Length */ 1268 #define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_MASK (0xffff) 1269 #define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_SHIFT 0 1270 1271 /* DSI_PHY_TIME_2 0x00c8 DPHY Timing Control Register 2 */ 1272 /* DPHY CLK Exit Period Length */ 1273 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_MASK (0xff<<24) 1274 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT 24 1275 /* DPHY CLK Trail Period Length */ 1276 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_MASK (0xff<<16) 1277 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT 16 1278 /* DPHY CLK Zero State Length */ 1279 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_MASK (0xff<<8) 1280 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT 8 1281 /* DPHY CLK LP Length */ 1282 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_MASK (0xff) 1283 #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_SHIFT 0 1284 1285 /* DSI_PHY_TIME_3 0x00cc DPHY Timing Control Register 3 */ 1286 /* Bit(s) DSI_PHY_TIME_3_RSRV_31_16 reserved */ 1287 /* DPHY LP Length */ 1288 #define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_MASK (0xff<<8) 1289 #define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT 8 1290 /* DPHY HS req to rdy Length */ 1291 #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff) 1292 #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0 1293 1294 #define DSI_ESC_CLK 66 /* Unit: Mhz */ 1295 #define DSI_ESC_CLK_T 15 /* Unit: ns */ 1296 1297 /* LVDS */ 1298 /* LVDS_PHY_CTRL */ 1299 #define LVDS_PHY_CTL 0x2A4 1300 #define LVDS_PLL_LOCK (1 << 31) 1301 #define LVDS_PHY_EXT_MASK (7 << 28) 1302 #define LVDS_PHY_EXT_SHIFT (28) 1303 #define LVDS_CLK_PHASE_MASK (0x7f << 16) 1304 #define LVDS_CLK_PHASE_SHIFT (16) 1305 #define LVDS_SSC_RESET_EXT (1 << 13) 1306 #define LVDS_SSC_MODE_DOWN_SPREAD (1 << 12) 1307 #define LVDS_SSC_EN (1 << 11) 1308 #define LVDS_PU_PLL (1 << 10) 1309 #define LVDS_PU_TX (1 << 9) 1310 #define LVDS_PU_IVREF (1 << 8) 1311 #define LVDS_CLK_SEL (1 << 7) 1312 #define LVDS_CLK_SEL_LVDS_PCLK (1 << 7) 1313 #define LVDS_PD_CH_MASK (0x3f << 1) 1314 #define LVDS_PD_CH(ch) ((ch) << 1) 1315 #define LVDS_RST (1 << 0) 1316 1317 #define LVDS_PHY_CTL_EXT 0x2A8 1318 1319 /* LVDS_PHY_CTRL_EXT1 */ 1320 #define LVDS_SSC_RNGE_MASK (0x7ff << 16) 1321 #define LVDS_SSC_RNGE_SHIFT (16) 1322 #define LVDS_RESERVE_IN_MASK (0xf << 12) 1323 #define LVDS_RESERVE_IN_SHIFT (12) 1324 #define LVDS_TEST_MON_MASK (0x7 << 8) 1325 #define LVDS_TEST_MON_SHIFT (8) 1326 #define LVDS_POL_SWAP_MASK (0x3f << 0) 1327 #define LVDS_POL_SWAP_SHIFT (0) 1328 1329 /* LVDS_PHY_CTRL_EXT2 */ 1330 #define LVDS_TX_DIF_AMP_MASK (0xf << 24) 1331 #define LVDS_TX_DIF_AMP_SHIFT (24) 1332 #define LVDS_TX_DIF_CM_MASK (0x3 << 22) 1333 #define LVDS_TX_DIF_CM_SHIFT (22) 1334 #define LVDS_SELLV_TXCLK_MASK (0x1f << 16) 1335 #define LVDS_SELLV_TXCLK_SHIFT (16) 1336 #define LVDS_TX_CMFB_EN (0x1 << 15) 1337 #define LVDS_TX_TERM_EN (0x1 << 14) 1338 #define LVDS_SELLV_TXDATA_MASK (0x1f << 8) 1339 #define LVDS_SELLV_TXDATA_SHIFT (8) 1340 #define LVDS_SELLV_OP7_MASK (0x3 << 6) 1341 #define LVDS_SELLV_OP7_SHIFT (6) 1342 #define LVDS_SELLV_OP6_MASK (0x3 << 4) 1343 #define LVDS_SELLV_OP6_SHIFT (4) 1344 #define LVDS_SELLV_OP9_MASK (0x3 << 2) 1345 #define LVDS_SELLV_OP9_SHIFT (2) 1346 #define LVDS_STRESSTST_EN (0x1 << 0) 1347 1348 /* LVDS_PHY_CTRL_EXT3 */ 1349 #define LVDS_KVCO_MASK (0xf << 28) 1350 #define LVDS_KVCO_SHIFT (28) 1351 #define LVDS_CTUNE_MASK (0x3 << 26) 1352 #define LVDS_CTUNE_SHIFT (26) 1353 #define LVDS_VREG_IVREF_MASK (0x3 << 24) 1354 #define LVDS_VREG_IVREF_SHIFT (24) 1355 #define LVDS_VDDL_MASK (0xf << 20) 1356 #define LVDS_VDDL_SHIFT (20) 1357 #define LVDS_VDDM_MASK (0x3 << 18) 1358 #define LVDS_VDDM_SHIFT (18) 1359 #define LVDS_FBDIV_MASK (0xf << 8) 1360 #define LVDS_FBDIV_SHIFT (8) 1361 #define LVDS_REFDIV_MASK (0x7f << 0) 1362 #define LVDS_REFDIV_SHIFT (0) 1363 1364 /* LVDS_PHY_CTRL_EXT4 */ 1365 #define LVDS_SSC_FREQ_DIV_MASK (0xffff << 16) 1366 #define LVDS_SSC_FREQ_DIV_SHIFT (16) 1367 #define LVDS_INTPI_MASK (0xf << 12) 1368 #define LVDS_INTPI_SHIFT (12) 1369 #define LVDS_VCODIV_SEL_SE_MASK (0xf << 8) 1370 #define LVDS_VCODIV_SEL_SE_SHIFT (8) 1371 #define LVDS_RESET_INTP_EXT (0x1 << 7) 1372 #define LVDS_VCO_VRNG_MASK (0x7 << 4) 1373 #define LVDS_VCO_VRNG_SHIFT (4) 1374 #define LVDS_PI_EN (0x1 << 3) 1375 #define LVDS_ICP_MASK (0x7 << 0) 1376 #define LVDS_ICP_SHIFT (0) 1377 1378 /* LVDS_PHY_CTRL_EXT5 */ 1379 #define LVDS_FREQ_OFFSET_MASK (0x1ffff << 15) 1380 #define LVDS_FREQ_OFFSET_SHIFT (15) 1381 #define LVDS_FREQ_OFFSET_VALID (0x1 << 2) 1382 #define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1) 1383 #define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0) 1384 1385 enum { 1386 PATH_PN = 0, 1387 PATH_TV, 1388 PATH_P2, 1389 }; 1390 1391 /* 1392 * mmp path describes part of mmp path related info: 1393 * which is hiden in display driver and not exported to buffer driver 1394 */ 1395 struct mmphw_ctrl; 1396 struct mmphw_path_plat { 1397 int id; 1398 struct mmphw_ctrl *ctrl; 1399 struct mmp_path *path; 1400 u32 path_config; 1401 u32 link_config; 1402 u32 dsi_rbswap; 1403 }; 1404 1405 /* mmp ctrl describes mmp controller related info */ 1406 struct mmphw_ctrl { 1407 /* platform related, get from config */ 1408 const char *name; 1409 int irq; 1410 void *reg_base; 1411 struct clk *clk; 1412 1413 /* sys info */ 1414 struct device *dev; 1415 1416 /* state */ 1417 int open_count; 1418 int status; 1419 struct mutex access_ok; 1420 1421 /*pathes*/ 1422 int path_num; 1423 struct mmphw_path_plat path_plats[0]; 1424 }; 1425 overlay_is_vid(struct mmp_overlay * overlay)1426 static inline int overlay_is_vid(struct mmp_overlay *overlay) 1427 { 1428 return overlay->dmafetch_id & 1; 1429 } 1430 path_to_path_plat(struct mmp_path * path)1431 static inline struct mmphw_path_plat *path_to_path_plat(struct mmp_path *path) 1432 { 1433 return (struct mmphw_path_plat *)path->plat_data; 1434 } 1435 path_to_ctrl(struct mmp_path * path)1436 static inline struct mmphw_ctrl *path_to_ctrl(struct mmp_path *path) 1437 { 1438 return path_to_path_plat(path)->ctrl; 1439 } 1440 overlay_to_ctrl(struct mmp_overlay * overlay)1441 static inline struct mmphw_ctrl *overlay_to_ctrl(struct mmp_overlay *overlay) 1442 { 1443 return path_to_ctrl(overlay->path); 1444 } 1445 ctrl_regs(struct mmp_path * path)1446 static inline void *ctrl_regs(struct mmp_path *path) 1447 { 1448 return path_to_ctrl(path)->reg_base; 1449 } 1450 1451 /* path regs, for regs symmetrical for both pathes */ path_regs(struct mmp_path * path)1452 static inline struct lcd_regs *path_regs(struct mmp_path *path) 1453 { 1454 if (path->id == PATH_PN) 1455 return (struct lcd_regs *)(ctrl_regs(path) + 0xc0); 1456 else if (path->id == PATH_TV) 1457 return (struct lcd_regs *)ctrl_regs(path); 1458 else if (path->id == PATH_P2) 1459 return (struct lcd_regs *)(ctrl_regs(path) + 0x200); 1460 else { 1461 dev_err(path->dev, "path id %d invalid\n", path->id); 1462 BUG_ON(1); 1463 return NULL; 1464 } 1465 } 1466 1467 #ifdef CONFIG_MMP_DISP_SPI 1468 extern int lcd_spi_register(struct mmphw_ctrl *ctrl); 1469 #endif 1470 #endif /* _MMP_CTRL_H_ */ 1471
