Searched refs:DP_TRAIN_PRE_EMPHASIS_MASK (Results 1 – 6 of 6) sorted by relevance
237 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); in amdgpu_atombios_dp_get_adjust_train()651 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()704 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in amdgpu_atombios_dp_link_train_ce()
287 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); in dp_get_adjust_train()729 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()780 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in radeon_dp_link_train_ce()
395 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) macro
3275 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_signal_levels()3361 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_signal_levels()3457 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in g4x_signal_levels()3480 DP_TRAIN_PRE_EMPHASIS_MASK); in snb_cpu_edp_signal_levels()3508 DP_TRAIN_PRE_EMPHASIS_MASK); in ivb_cpu_edp_signal_levels()3569 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> in intel_dp_set_signal_levels()
2502 DP_TRAIN_PRE_EMPHASIS_MASK); in intel_ddi_dp_level()
1325 if (p == DP_TRAIN_PRE_EMPHASIS_MASK) in cdv_intel_get_adjust_train()1445 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >> in cdv_intel_dp_set_vswing_premph()
