Searched refs:DP_TP_CTL_LINK_TRAIN_PAT1 (Results 1 – 3 of 3) sorted by relevance
1155 DP_TP_CTL_LINK_TRAIN_PAT1 | in hsw_fdi_link_train()1217 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in hsw_fdi_link_train()2797 val |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_disable_ddi_buf()3092 val |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_ddi_prepare_link_retrain()3101 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; in intel_ddi_prepare_link_retrain()
2891 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in _intel_dp_set_link_train()
9039 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) macro
