Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 7 of 7) sorted by relevance
236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()673 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
163 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
244 #define DPLL_VGA_MODE_DIS (1 << 28) macro
531 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()1589 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()1601 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_disable_pll()1618 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()6871 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_compute_dpll()6888 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_compute_dpll()7169 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()7243 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()15297 DPLL_VGA_MODE_DIS | in i830_enable_pipe()15319 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()[all …]
996 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
3201 #define DPLL_VGA_MODE_DIS (1 << 28) macro
