Searched refs:DPLL_CFGCR0_HDMI_MODE (Results 1 – 3 of 3) sorted by relevance
1996 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_pll_enable()2117 if (val & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_pll_get_hw_state()2277 cfgcr0 = DPLL_CFGCR0_HDMI_MODE; in cnl_ddi_hdmi_pll_dividers()
1490 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_clock_get()
9477 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) macro
