Searched refs:DMA_CHAN_RX_CONTROL (Results 1 – 3 of 3) sorted by relevance
74 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()78 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()87 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()90 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()
81 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()83 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()148 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = in _dwmac4_dump_dma_regs()149 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); in _dwmac4_dump_dma_regs()425 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_set_bfsize()430 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_set_bfsize()
97 #define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8) macro
