Searched refs:DMA1_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
64 reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_rptr()88 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_wptr()109 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_set_wptr()171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()202 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
868 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in cayman_get_allowed_info_register()1130 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()1771 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()1854 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()1856 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1319 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in si_get_allowed_info_register()3279 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()3803 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()3886 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()3888 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()4051 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()4053 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()5537 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()5549 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()5956 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()[all …]
1302 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
1813 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
33 DMA1_REGISTER_OFFSET629 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()631 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()634 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()636 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()690 offset = DMA1_REGISTER_OFFSET; in si_dma_set_clockgating_state()702 offset = DMA1_REGISTER_OFFSET; in si_dma_set_clockgating_state()
113 #define DMA1_REGISTER_OFFSET 0x200 macro
1876 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_gpu_init()
