Searched refs:DMA0_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | ni_dma.c | 62 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_rptr()
86 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_wptr()
107 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_set_wptr()
166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
198 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
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| D | ni.c | 867 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in cayman_get_allowed_info_register()
1129 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1766 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()
1847 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1849 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
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| D | si.c | 1318 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in si_get_allowed_info_register()
3278 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3798 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3880 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3882 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4047 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4049 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5535 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5547 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5954 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
[all …]
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| D | nid.h | 1301 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| D | sid.h | 1812 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | si_dma.c | 32 DMA0_REGISTER_OFFSET,
613 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
615 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
618 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
620 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
688 offset = DMA0_REGISTER_OFFSET; in si_dma_set_clockgating_state()
700 offset = DMA0_REGISTER_OFFSET; in si_dma_set_clockgating_state()
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| D | si_enums.h | 112 #define DMA0_REGISTER_OFFSET 0x000 macro
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| D | sid.h | 1875 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| D | gfx_v6_0.c | 1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_gpu_init()
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