Searched refs:DISPLAY_PLANE_ENABLE (Results 1 – 12 of 12) sorted by relevance
253 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_disable_crtc()255 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_disable_crtc()365 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in mdfld_crtc_dpms()367 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()393 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()409 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()441 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_crtc_dpms()443 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()859 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
358 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()392 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()393 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()460 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()461 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
277 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_dpms()279 temp | DISPLAY_PLANE_ENABLE, in oaktrail_crtc_dpms()303 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_dpms()305 temp & ~DISPLAY_PLANE_ENABLE, i); in oaktrail_crtc_dpms()
239 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in gma_crtc_dpms()241 temp | DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()286 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in gma_crtc_dpms()288 temp & ~DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
357 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); in mdfld_restore_display_registers()
212 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
636 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
733 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
297 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
216 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); in intel_vgpu_decode_primary_plane()
3221 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; in i9xx_plane_ctl()3413 ret = val & DISPLAY_PLANE_ENABLE; in i9xx_plane_get_hw_state()15353 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()15354 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()15355 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
6118 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
