Searched refs:DGCS (Results 1 – 2 of 2) sorted by relevance
104 val = ioread32(bridge->base + DGCS); in ca91cx42_VERR_irqhandler()121 val = ioread32(bridge->base + DGCS); in ca91cx42_LERR_irqhandler()1173 tmp = ioread32(bridge->base + DGCS); in ca91cx42_dma_busy()1223 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()1232 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()1236 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()1242 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()1243 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); in ca91cx42_dma_list_exec()1255 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
150 #define DGCS 0x0220 macro
