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Searched refs:DCLK (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/
Dpower_state.h137 uint32_t DCLK; member
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dst,nomadik.txt99 58: 3DCLK
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dprocesspptables.c761 ps->uvd_clocks.DCLK = pnon_clock_info->ulDCLK; in init_non_clock_fields()
764 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
Dsmu10_hwmgr.c760 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
Dsmu7_hwmgr.c3158 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3251 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()
3399 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
Dsmu8_hwmgr.c1383 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
Dvega10_hwmgr.c3017 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3084 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
/Linux-v4.19/drivers/gpu/drm/i915/
Di915_reg.h3518 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro
Dintel_pm.c7128 min_ring_freq = I915_READ(DCLK) & 0xf; in gen6_update_ring_freq()