Searched refs:DCCG_AUDIO_DTO1_PHASE (Results 1 – 10 of 10) sorted by relevance
40 SR(DCCG_AUDIO_DTO1_PHASE)55 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\78 uint32_t DCCG_AUDIO_DTO1_PHASE; member96 uint8_t DCCG_AUDIO_DTO1_PHASE; member113 uint32_t DCCG_AUDIO_DTO1_PHASE; member
857 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, in dce_aud_wall_dto_setup()858 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); in dce_aud_wall_dto_setup()
164 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); in dce3_2_audio_set_dto()
315 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); in dce6_dp_audio_set_dto()
334 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); in r600_hdmi_audio_set_dto()
302 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); in dce4_dp_audio_set_dto()
915 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 macro
508 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 macro
962 #define DCCG_AUDIO_DTO1_PHASE 0x0524 macro
919 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 macro
