Searched refs:CSR0_INEA (Results 1 – 4 of 4) sorted by relevance
218 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ macro442 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; in lance_open()559 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_start_xmit()635 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; in lance_start_xmit()720 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()758 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()766 REGA(CSR0) = CSR0_INEA; in lance_interrupt()932 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
318 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ macro669 DREG = CSR0_INEA; in lance_open()765 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_tx_timeout()834 DREG = CSR0_INEA | CSR0_TDMD; in lance_start_xmit()872 CSR0_TDMD | CSR0_INEA); in lance_interrupt()950 CSR0_IDON | CSR0_INEA; in lance_interrupt()1106 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
28 #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */ macro
537 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ in ni65_probe1()725 int csr0 = CSR0_INEA; in ni65_stop_start()774 writedatareg(CSR0_TDMD | CSR0_INEA | csr0); in ni65_stop_start()862 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT); in ni65_lance_reinit()892 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */ in ni65_interrupt()974 writedatareg(CSR0_INEA); in ni65_interrupt()1204 writedatareg(CSR0_TDMD | CSR0_INEA); /* enable xmit & interrupt */ in ni65_send_packet()
