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Searched refs:CSR (Results 1 – 25 of 58) sorted by relevance

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/Linux-v4.19/arch/arm/mach-prima2/
DKconfig2 bool "CSR SiRF"
13 Support for CSR SiRFprimaII/Marco/Polo platforms
17 comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
20 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
24 Support for CSR SiRFSoC ARM Cortex A9 Platform
27 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
34 Support for CSR SiRFSoC ARM Cortex A7 Platform
37 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
43 Support for CSR SiRFSoC ARM Cortex A9 Platform
/Linux-v4.19/arch/arm/boot/dts/
Dprima2-evb.dts2 * DTS file for CSR SiRFprimaII Evaluation Board
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
14 model = "CSR SiRFprimaII Evaluation Board";
Datlas6-evb.dts2 * DTS file for CSR SiRFatlas6 Evaluation Board
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
14 model = "CSR SiRFatlas6 Evaluation Board";
Datlas7-evb.dts2 * DTS file for CSR SiRFatlas7 Evaluation Board
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
17 model = "CSR SiRFatlas7 Evaluation Board";
/Linux-v4.19/drivers/scsi/aacraid/
Daacraid.h1093 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1094 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1095 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1096 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1155 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1156 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1157 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1158 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
1173 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1174 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
/Linux-v4.19/arch/c6x/kernel/
Dentry.S31 MVC .S2 CSR,reg
33 MVC .S2 reg,CSR
37 MVC .S2 CSR,reg
39 MVC .S2 reg,CSR
77 || MVC .S2 CSR,B12
114 STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
130 LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
170 || MVC .S2 B12,CSR
248 MVC .S2 CSR,B1
250 MVC .S2 B1,CSR ; enable ints
Dhead.S45 MVC .S2 CSR,B2
47 MVC .S2 B2,CSR
/Linux-v4.19/drivers/dma/
Dtxx9dmac.c299 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
311 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
353 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
374 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
484 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
497 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
523 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
549 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
550 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
Dtxx9dmac.h81 TXX9_DMA_REG32(CSR); /* Channel Status Register */
91 u32 CSR; member
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dxgene.txt36 - reg : shall be a list of address and length pairs describing the CSR
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
Dprima2-clock.txt1 * Clock bindings for CSR SiRFprimaII
Dcsr,atlas7-car.txt1 * Clock and reset bindings for CSR atlas7
/Linux-v4.19/drivers/net/ethernet/qlogic/qlge/
Dqlge_mpi.c9 tmp = ql_read32(qdev, CSR); in ql_unpause_mpi_risc()
13 ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in ql_unpause_mpi_risc()
23 ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in ql_pause_mpi_risc()
25 tmp = ql_read32(qdev, CSR); in ql_pause_mpi_risc()
40 ql_write32(qdev, CSR, CSR_CMD_SET_RST); in ql_hard_reset_mpi_risc()
42 tmp = ql_read32(qdev, CSR); in ql_hard_reset_mpi_risc()
44 ql_write32(qdev, CSR, CSR_CMD_CLR_RST); in ql_hard_reset_mpi_risc()
175 if (ql_read32(qdev, CSR) & CSR_HRI) in ql_exec_mb_cmd()
194 ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in ql_exec_mb_cmd()
516 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in ql_mpi_handler()
[all …]
/Linux-v4.19/arch/arm/plat-omap/
Ddma.c499 p->dma_read(CSR, lch); in omap_enable_channel_irq()
501 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_enable_channel_irq()
513 p->dma_read(CSR, lch); in omap_disable_channel_irq()
515 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_disable_channel_irq()
1099 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
1151 u32 status = p->dma_read(CSR, ch); in omap2_dma_handle_ch()
1187 p->dma_write(status, CSR, ch); in omap2_dma_handle_ch()
1206 status = p->dma_read(CSR, ch); in omap2_dma_handle_ch()
1207 p->dma_write(status, CSR, ch); in omap2_dma_handle_ch()
/Linux-v4.19/Documentation/devicetree/bindings/arm/
Dsirf.txt1 CSR SiRFprimaII and SiRFmarco device tree bindings.
/Linux-v4.19/Documentation/devicetree/bindings/pci/
Daltera-pcie-msi.txt8 "csr": CSR registers
/Linux-v4.19/Documentation/devicetree/bindings/gpio/
Dgpio-atlas7.txt1 CSR SiRFatlas7 GPIO controller bindings
/Linux-v4.19/Documentation/devicetree/bindings/serial/
Dsirf-uart.txt1 * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
/Linux-v4.19/arch/arm/mach-omap1/
Ddma.c62 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
222 l = dma_read(CSR, lch); in omap1_clear_dma()
/Linux-v4.19/Documentation/devicetree/bindings/misc/
Didt_89hpesx.txt1 EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
/Linux-v4.19/Documentation/devicetree/bindings/dma/
Dsirfsoc-dma.txt1 * CSR SiRFSoC DMA controller
/Linux-v4.19/Documentation/devicetree/bindings/reset/
Dsirf,rstc.txt1 CSR SiRFSoC Reset Controller
/Linux-v4.19/Documentation/devicetree/bindings/spi/
Dspi-sirf.txt1 * CSR SiRFprimaII Serial Peripheral Interface
/Linux-v4.19/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-sirf.txt1 CSR SiRFprimaII pinmux controller
Dpinctrl-atlas7.txt1 CSR SiRFatlas7 pinmux controller

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