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Searched refs:CP_RB0_CNTL (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/radeon/
Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
Dsid.h1246 #define CP_RB0_CNTL 0xC104 macro
Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
Dsi.c3670 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3673 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3689 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
Dni.c1629 CP_RB0_CNTL, in cayman_cp_resume()
Dcik.c4084 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4087 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4102 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsid.h1275 #define CP_RB0_CNTL 0x3041 macro
Dgfx_v8_0.c4487 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4488 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4489 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4490 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4492 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
Dgfx_v9_0.c2483 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
2484 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
2486 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()