Searched refs:CPG_PLL0CR (Results 1 – 5 of 5) sorted by relevance
30 #define CPG_PLL0CR 0xd8 macro98 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
32 #define CPG_PLL0CR 0xd8 macro99 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
27 #define CPG_PLL0CR 0x00d8 macro310 u32 pll0cr = readl(base + CPG_PLL0CR); in rcar_gen2_cpg_clk_register()
33 #define CPG_PLL0CR 0x000000d8 macro334 u32 value = readl(cpg->reg + CPG_PLL0CR); in rcar_gen2_cpg_register_clock()
30 #define CPG_PLL0CR 0x00d8 macro463 value = readl(base + CPG_PLL0CR); in rcar_gen3_cpg_clk_register()
