1 /*
2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@mips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11 #ifndef __MIPS_ASM_MIPS_CPS_H__
12 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
13 #endif
14
15 #ifndef __MIPS_ASM_MIPS_CM_H__
16 #define __MIPS_ASM_MIPS_CM_H__
17
18 #include <linux/bitops.h>
19 #include <linux/errno.h>
20
21 /* The base address of the CM GCR block */
22 extern void __iomem *mips_gcr_base;
23
24 /* The base address of the CM L2-only sync region */
25 extern void __iomem *mips_cm_l2sync_base;
26
27 /**
28 * __mips_cm_phys_base - retrieve the physical base address of the CM
29 *
30 * This function returns the physical base address of the Coherence Manager
31 * global control block, or 0 if no Coherence Manager is present. It provides
32 * a default implementation which reads the CMGCRBase register where available,
33 * and may be overridden by platforms which determine this address in a
34 * different way by defining a function with the same prototype except for the
35 * name mips_cm_phys_base (without underscores).
36 */
37 extern phys_addr_t __mips_cm_phys_base(void);
38
39 /*
40 * mips_cm_is64 - determine CM register width
41 *
42 * The CM register width is determined by the version of the CM, with CM3
43 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
44 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
45 * or vice-versa. This variable indicates the width of the memory accesses
46 * that the kernel will perform to GCRs, which may differ from the actual
47 * width of the GCRs.
48 *
49 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
50 */
51 extern int mips_cm_is64;
52
53 /**
54 * mips_cm_error_report - Report CM cache errors
55 */
56 #ifdef CONFIG_MIPS_CM
57 extern void mips_cm_error_report(void);
58 #else
mips_cm_error_report(void)59 static inline void mips_cm_error_report(void) {}
60 #endif
61
62 /**
63 * mips_cm_probe - probe for a Coherence Manager
64 *
65 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
66 * is successfully detected, else -errno.
67 */
68 #ifdef CONFIG_MIPS_CM
69 extern int mips_cm_probe(void);
70 #else
mips_cm_probe(void)71 static inline int mips_cm_probe(void)
72 {
73 return -ENODEV;
74 }
75 #endif
76
77 /**
78 * mips_cm_present - determine whether a Coherence Manager is present
79 *
80 * Returns true if a CM is present in the system, else false.
81 */
mips_cm_present(void)82 static inline bool mips_cm_present(void)
83 {
84 #ifdef CONFIG_MIPS_CM
85 return mips_gcr_base != NULL;
86 #else
87 return false;
88 #endif
89 }
90
91 /**
92 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
93 *
94 * Returns true if the system implements an L2-only sync region, else false.
95 */
mips_cm_has_l2sync(void)96 static inline bool mips_cm_has_l2sync(void)
97 {
98 #ifdef CONFIG_MIPS_CM
99 return mips_cm_l2sync_base != NULL;
100 #else
101 return false;
102 #endif
103 }
104
105 /* Offsets to register blocks from the CM base address */
106 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
107 #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
108 #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
109 #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
110
111 /* Total size of the CM memory mapped registers */
112 #define MIPS_CM_GCR_SIZE 0x8000
113
114 /* Size of the L2-only sync region */
115 #define MIPS_CM_L2SYNC_SIZE 0x1000
116
117 #define GCR_ACCESSOR_RO(sz, off, name) \
118 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
119 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
120
121 #define GCR_ACCESSOR_RW(sz, off, name) \
122 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
123 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
124
125 #define GCR_CX_ACCESSOR_RO(sz, off, name) \
126 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
127 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
128
129 #define GCR_CX_ACCESSOR_RW(sz, off, name) \
130 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
131 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
132
133 /* GCR_CONFIG - Information about the system */
134 GCR_ACCESSOR_RO(64, 0x000, config)
135 #define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
136 #define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
137 #define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
138 #define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
139 #define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
140
141 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
142 GCR_ACCESSOR_RW(64, 0x008, base)
143 #define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
144 #define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
145 #define CM_GCR_BASE_CMDEFTGT_MEM 0
146 #define CM_GCR_BASE_CMDEFTGT_RESERVED 1
147 #define CM_GCR_BASE_CMDEFTGT_IOCU0 2
148 #define CM_GCR_BASE_CMDEFTGT_IOCU1 3
149
150 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
151 GCR_ACCESSOR_RW(32, 0x020, access)
152 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
153
154 /* GCR_REV - Indicates the Coherence Manager revision */
155 GCR_ACCESSOR_RO(32, 0x030, rev)
156 #define CM_GCR_REV_MAJOR GENMASK(15, 8)
157 #define CM_GCR_REV_MINOR GENMASK(7, 0)
158
159 #define CM_ENCODE_REV(major, minor) \
160 (((major) << __ffs(CM_GCR_REV_MAJOR)) | \
161 ((minor) << __ffs(CM_GCR_REV_MINOR)))
162
163 #define CM_REV_CM2 CM_ENCODE_REV(6, 0)
164 #define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
165 #define CM_REV_CM3 CM_ENCODE_REV(8, 0)
166 #define CM_REV_CM3_5 CM_ENCODE_REV(9, 0)
167
168 /* GCR_ERR_CONTROL - Control error checking logic */
169 GCR_ACCESSOR_RW(32, 0x038, err_control)
170 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
171 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
172
173 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
174 GCR_ACCESSOR_RW(64, 0x040, error_mask)
175
176 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
177 GCR_ACCESSOR_RW(64, 0x048, error_cause)
178 #define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
179 #define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
180 #define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
181
182 /* GCR_ERR_ADDR - Indicates the address associated with an error */
183 GCR_ACCESSOR_RW(64, 0x050, error_addr)
184
185 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
186 GCR_ACCESSOR_RW(64, 0x058, error_mult)
187 #define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
188
189 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
190 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
191 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
192 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
193
194 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
195 GCR_ACCESSOR_RW(64, 0x080, gic_base)
196 #define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
197 #define CM_GCR_GIC_BASE_GICEN BIT(0)
198
199 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
200 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
201 #define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
202 #define CM_GCR_CPC_BASE_CPCEN BIT(0)
203
204 /* GCR_REGn_BASE - Base addresses of CM address regions */
205 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
206 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
207 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
208 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
209 #define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
210
211 /* GCR_REGn_MASK - Size & destination of CM address regions */
212 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
213 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
214 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
215 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
216 #define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
217 #define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
218 #define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
219 #define CM_GCR_REGn_MASK_DROPL2 BIT(2)
220 #define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
221 #define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0
222 #define CM_GCR_REGn_MASK_CMTGT_MEM 0x1
223 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2
224 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3
225
226 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
227 GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
228 #define CM_GCR_GIC_STATUS_EX BIT(0)
229
230 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
231 GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
232 #define CM_GCR_CPC_STATUS_EX BIT(0)
233
234 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
235 GCR_ACCESSOR_RW(32, 0x130, l2_config)
236 #define CM_GCR_L2_CONFIG_BYPASS BIT(20)
237 #define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
238 #define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
239 #define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
240
241 /* GCR_SYS_CONFIG2 - Further information about the system */
242 GCR_ACCESSOR_RO(32, 0x150, sys_config2)
243 #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
244
245 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
246 GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
247 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
248 #define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
249 #define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
250
251 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
252 GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
253 #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
254 #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
255
256 /* GCR_L2SM_COP - L2 cache op state machine control */
257 GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
258 #define CM_GCR_L2SM_COP_PRESENT BIT(31)
259 #define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
260 #define CM_GCR_L2SM_COP_RESULT_DONTCARE 0
261 #define CM_GCR_L2SM_COP_RESULT_DONE_OK 1
262 #define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2
263 #define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3
264 #define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
265 #define CM_GCR_L2SM_COP_RUNNING BIT(5)
266 #define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
267 #define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0
268 #define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1
269 #define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2
270 #define CM_GCR_L2SM_COP_TYPE_HIT_INV 4
271 #define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5
272 #define CM_GCR_L2SM_COP_TYPE_HIT_WB 6
273 #define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7
274 #define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
275 #define CM_GCR_L2SM_COP_CMD_START 1 /* only when idle */
276 #define CM_GCR_L2SM_COP_CMD_ABORT 3 /* only when running */
277
278 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
279 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
280 #define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
281 #define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)
282
283 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
284 GCR_ACCESSOR_RW(64, 0x680, bev_base)
285
286 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
287 GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
288
289 /* GCR_Cx_COHERENCE - Controls core coherence */
290 GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
291 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
292 #define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
293
294 /* GCR_Cx_CONFIG - Information about a core's configuration */
295 GCR_CX_ACCESSOR_RO(32, 0x010, config)
296 #define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
297 #define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
298
299 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
300 GCR_CX_ACCESSOR_RW(32, 0x018, other)
301 #define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */
302 #define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
303 #define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
304 #define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */
305 #define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0
306 #define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1
307 #define CM_GCR_Cx_OTHER_BLOCK_USER 2
308 #define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3
309 #define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */
310 #define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */
311 #define CM_GCR_Cx_OTHER_CORE_CM 32
312 #define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */
313
314 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
315 GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
316 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
317
318 /* GCR_Cx_ID - Identify the current core */
319 GCR_CX_ACCESSOR_RO(32, 0x028, id)
320 #define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
321 #define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
322
323 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
324 GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
325 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
326 #define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
327 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
328 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
329 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
330
331 /**
332 * mips_cm_l2sync - perform an L2-only sync operation
333 *
334 * If an L2-only sync region is present in the system then this function
335 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
336 */
mips_cm_l2sync(void)337 static inline int mips_cm_l2sync(void)
338 {
339 if (!mips_cm_has_l2sync())
340 return -ENODEV;
341
342 writel(0, mips_cm_l2sync_base);
343 return 0;
344 }
345
346 /**
347 * mips_cm_revision() - return CM revision
348 *
349 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
350 * return value should be checked against the CM_REV_* macros.
351 */
mips_cm_revision(void)352 static inline int mips_cm_revision(void)
353 {
354 if (!mips_cm_present())
355 return 0;
356
357 return read_gcr_rev();
358 }
359
360 /**
361 * mips_cm_max_vp_width() - return the width in bits of VP indices
362 *
363 * Return: the width, in bits, of VP indices in fields that combine core & VP
364 * indices.
365 */
mips_cm_max_vp_width(void)366 static inline unsigned int mips_cm_max_vp_width(void)
367 {
368 extern int smp_num_siblings;
369 uint32_t cfg;
370
371 if (mips_cm_revision() >= CM_REV_CM3)
372 return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
373
374 if (mips_cm_present()) {
375 /*
376 * We presume that all cores in the system will have the same
377 * number of VP(E)s, and if that ever changes then this will
378 * need revisiting.
379 */
380 cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
381 return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
382 }
383
384 if (IS_ENABLED(CONFIG_SMP))
385 return smp_num_siblings;
386
387 return 1;
388 }
389
390 /**
391 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
392 * @cpu: the CPU whose VP ID to calculate
393 *
394 * Hardware such as the GIC uses identifiers for VPs which may not match the
395 * CPU numbers used by Linux. This function calculates the hardware VP
396 * identifier corresponding to a given CPU.
397 *
398 * Return: the VP ID for the CPU.
399 */
mips_cm_vp_id(unsigned int cpu)400 static inline unsigned int mips_cm_vp_id(unsigned int cpu)
401 {
402 unsigned int core = cpu_core(&cpu_data[cpu]);
403 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
404
405 return (core * mips_cm_max_vp_width()) + vp;
406 }
407
408 #ifdef CONFIG_MIPS_CM
409
410 /**
411 * mips_cm_lock_other - lock access to redirect/other region
412 * @cluster: the other cluster to be accessed
413 * @core: the other core to be accessed
414 * @vp: the VP within the other core to be accessed
415 * @block: the register block to be accessed
416 *
417 * Configure the redirect/other region for the local core/VP (depending upon
418 * the CM revision) to target the specified @cluster, @core, @vp & register
419 * @block. Must be called before using the redirect/other region, and followed
420 * by a call to mips_cm_unlock_other() when access to the redirect/other region
421 * is complete.
422 *
423 * This function acquires a spinlock such that code between it &
424 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
425 * reconfigure the redirect/other region, and cannot be interfered with by
426 * another VP in the core. As such calls to this function should not be nested.
427 */
428 extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
429 unsigned int vp, unsigned int block);
430
431 /**
432 * mips_cm_unlock_other - unlock access to redirect/other region
433 *
434 * Must be called after mips_cm_lock_other() once all required access to the
435 * redirect/other region has been completed.
436 */
437 extern void mips_cm_unlock_other(void);
438
439 #else /* !CONFIG_MIPS_CM */
440
mips_cm_lock_other(unsigned int cluster,unsigned int core,unsigned int vp,unsigned int block)441 static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
442 unsigned int vp, unsigned int block) { }
mips_cm_unlock_other(void)443 static inline void mips_cm_unlock_other(void) { }
444
445 #endif /* !CONFIG_MIPS_CM */
446
447 /**
448 * mips_cm_lock_other_cpu - lock access to redirect/other region
449 * @cpu: the other CPU whose register we want to access
450 *
451 * Configure the redirect/other region for the local core/VP (depending upon
452 * the CM revision) to target the specified @cpu & register @block. This is
453 * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
454 * for convenience.
455 */
mips_cm_lock_other_cpu(unsigned int cpu,unsigned int block)456 static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
457 {
458 struct cpuinfo_mips *d = &cpu_data[cpu];
459
460 mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
461 }
462
463 #endif /* __MIPS_ASM_MIPS_CM_H__ */
464
