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Searched refs:CLK_UART2 (Results 1 – 25 of 28) sorted by relevance

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/Linux-v4.19/include/dt-bindings/clock/
Dexynos5410.h41 #define CLK_UART2 259 macro
Dactions,s700-cmu.h60 #define CLK_UART2 38 macro
Dactions,s900-cmu.h87 #define CLK_UART2 69 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos5420.h70 #define CLK_UART2 259 macro
Dexynos4.h155 #define CLK_UART2 314 macro
Dexynos3250.h231 #define CLK_UART2 222 macro
Dsprd,sc9860-clk.h87 #define CLK_UART2 4 macro
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dexynos5250-clock.txt39 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5420-clock.txt40 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos4-clock.txt41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
/Linux-v4.19/drivers/clk/samsung/
Dclk-exynos5410.c202 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
Dclk-s5pv210.c615 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
Dclk-exynos5250.c616 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
Dclk-exynos3250.c666 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
Dclk-exynos4.c997 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
Dclk-exynos5420.c1091 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
/Linux-v4.19/arch/arm/boot/dts/
Ds5pv210.dtsi359 clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
Dexynos5410.dtsi360 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos3250.dtsi505 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
Dexynos4.dtsi481 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
/Linux-v4.19/drivers/clk/actions/
Dowl-s700.c525 [CLK_UART2] = &clk_uart2.common.hw,
Dowl-s900.c676 [CLK_UART2] = &uart2_clk.common.hw,
/Linux-v4.19/drivers/clk/renesas/
Dr9a06g032-clocks.c295 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),

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