Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 – 8 of 8) sorted by relevance
| /Linux-v4.19/include/dt-bindings/clock/ |
| D | mt7622-clk.h | 87 #define CLK_TOP_MSDC50_0_SEL 67 macro
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| D | mt8173-clk.h | 114 #define CLK_TOP_MSDC50_0_SEL 96 macro
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| D | mt2712-clk.h | 151 #define CLK_TOP_MSDC50_0_SEL 112 macro
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| /Linux-v4.19/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.txt | 62 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-mt7622.c | 549 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
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| D | clk-mt2712.c | 771 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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| D | clk-mt8173.c | 567 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
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| /Linux-v4.19/arch/arm64/boot/dts/mediatek/ |
| D | mt7622.dtsi | 632 <&topckgen CLK_TOP_MSDC50_0_SEL>;
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