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Searched refs:CLK_TOP_AUD_INTBUS_SEL (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/include/dt-bindings/clock/
Dmt8135-clk.h86 #define CLK_TOP_AUD_INTBUS_SEL 67 macro
Dmt7622-clk.h93 #define CLK_TOP_AUD_INTBUS_SEL 73 macro
Dmt8173-clk.h119 #define CLK_TOP_AUD_INTBUS_SEL 101 macro
Dmt2712-clk.h156 #define CLK_TOP_AUD_INTBUS_SEL 117 macro
/Linux-v4.19/drivers/clk/mediatek/
Dclk-mt8135.c367 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt7622.c565 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt2712.c782 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
Dclk-mt8173.c573 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
/Linux-v4.19/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi754 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,