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Searched refs:CLK_SCLK_UART2 (Results 1 – 24 of 24) sorted by relevance

/Linux-v4.19/include/dt-bindings/clock/
Dexynos5410.h27 #define CLK_SCLK_UART2 130 macro
Dexynos5250.h47 #define CLK_SCLK_UART2 148 macro
Dexynos7-clk.h42 #define CLK_SCLK_UART2 5 macro
Dexynos5420.h34 #define CLK_SCLK_UART2 130 macro
Dexynos4.h69 #define CLK_SCLK_UART2 153 macro
Dexynos3250.h259 #define CLK_SCLK_UART2 248 macro
Dexynos5433.h438 #define CLK_SCLK_UART2 34 macro
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dexynos5250-clock.txt39 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5420-clock.txt40 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos4-clock.txt41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
/Linux-v4.19/drivers/clk/samsung/
Dclk-exynos5410.c218 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
Dclk-exynos5250.c536 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
Dclk-exynos3250.c566 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
Dclk-exynos7.c365 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
Dclk-exynos4.c926 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
Dclk-exynos5420.c1013 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
Dclk-exynos5433.c1689 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
/Linux-v4.19/arch/arm/boot/dts/
Dexynos5410.dtsi360 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos3250.dtsi505 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
Dexynos4.dtsi481 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5250.dtsi1115 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5420.dtsi1483 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
/Linux-v4.19/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi182 <&clock_top0 CLK_SCLK_UART2>,
Dexynos5433.dtsi1258 <&cmu_peric CLK_SCLK_UART2>;