Searched refs:CLK_SCLK_UART1 (Results 1 – 21 of 21) sorted by relevance
| /Linux-v4.19/include/dt-bindings/clock/ |
| D | exynos5410.h | 26 #define CLK_SCLK_UART1 129 macro
|
| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
|
| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
|
| D | exynos5420.h | 33 #define CLK_SCLK_UART1 129 macro
|
| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
|
| D | exynos3250.h | 257 #define CLK_SCLK_UART1 246 macro
|
| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
|
| /Linux-v4.19/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 216 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
|
| D | clk-exynos5250.c | 534 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
|
| D | clk-exynos3250.c | 568 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
|
| D | clk-exynos7.c | 367 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
|
| D | clk-exynos4.c | 924 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
|
| D | clk-exynos5420.c | 1011 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
|
| D | clk-exynos5433.c | 1692 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
|
| /Linux-v4.19/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 353 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
| D | exynos3250.dtsi | 494 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
|
| D | exynos4.dtsi | 470 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
| D | exynos5250.dtsi | 1108 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
| D | exynos5420.dtsi | 1476 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
| /Linux-v4.19/arch/arm64/boot/dts/exynos/ |
| D | exynos7.dtsi | 181 <&clock_top0 CLK_SCLK_UART1>,
|
| D | exynos5433.dtsi | 1246 <&cmu_peric CLK_SCLK_UART1>;
|
