Searched refs:CLK_PDMA0 (Results 1 – 21 of 21) sorted by relevance
| /Linux-v4.19/include/dt-bindings/clock/ |
| D | exynos5410.h | 59 #define CLK_PDMA0 362 macro
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| D | exynos5250.h | 81 #define CLK_PDMA0 275 macro
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| D | s5pv210.h | 118 #define CLK_PDMA0 97 macro
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| D | exynos5420.h | 124 #define CLK_PDMA0 362 macro
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| D | exynos4.h | 133 #define CLK_PDMA0 292 macro
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| D | exynos3250.h | 210 #define CLK_PDMA0 201 macro
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| D | exynos5433.h | 575 #define CLK_PDMA0 65 macro
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| /Linux-v4.19/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 186 GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
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| D | clk-s5pv210.c | 592 GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
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| D | clk-exynos5250.c | 597 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
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| D | clk-exynos3250.c | 650 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
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| D | clk-exynos4.c | 980 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
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| D | clk-exynos5420.c | 1071 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
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| D | clk-exynos5433.c | 2299 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 203 clocks = <&clock CLK_PDMA0>;
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| D | s5pv210.dtsi | 140 clocks = <&clocks CLK_PDMA0>;
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| D | exynos3250.dtsi | 426 clocks = <&cmu CLK_PDMA0>;
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| D | exynos4.dtsi | 689 clocks = <&clock CLK_PDMA0>;
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| D | exynos5250.dtsi | 631 clocks = <&clock CLK_PDMA0>;
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| D | exynos5420.dtsi | 376 clocks = <&clock CLK_PDMA0>;
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| /Linux-v4.19/arch/arm64/boot/dts/exynos/ |
| D | exynos5433.dtsi | 1676 clocks = <&cmu_fsys CLK_PDMA0>;
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