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Searched refs:CHL_INT0 (Results 1 – 3 of 3) sorted by relevance

/Linux-v4.19/drivers/scsi/hisi_sas/
Dhisi_sas_v1_hw.c162 #define CHL_INT0 (PORT_BASE + 0x1b0) macro
1444 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); in int_phyup_v1_hw()
1447 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0); in int_phyup_v1_hw()
1498 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); in int_abnormal_v1_hw()
1527 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value); in int_abnormal_v1_hw()
1763 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); in interrupt_openall_v1_hw()
1764 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); in interrupt_openall_v1_hw()
Dhisi_sas_v3_hw.c158 #define CHL_INT0 (PORT_BASE + 0x1b4) macro
476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); in init_reg_v3_hw()
1253 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_up_v3_hw()
1279 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); in phy_down_v3_hw()
1297 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_bcast_v3_hw()
1316 CHL_INT0); in int_phy_up_down_bcast_v3_hw()
1444 CHL_INT0); in int_chnl_int_v3_hw()
1454 CHL_INT0, irq_value0 in int_chnl_int_v3_hw()
Dhisi_sas_v2_hw.c228 #define CHL_INT0 (PORT_BASE + 0x1b4) macro
1245 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); in init_reg_v2_hw()
2730 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_up_v2_hw()
2773 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); in phy_down_v2_hw()
2791 CHL_INT0); in int_phy_updown_v2_hw()
2851 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_bcast_v2_hw()
2900 CHL_INT0); in int_chnl_int_v2_hw()
2944 CHL_INT0, irq_value0 in int_chnl_int_v2_hw()