Searched refs:CCR2 (Results 1 – 6 of 6) sorted by relevance
| /Linux-v4.19/drivers/net/wan/ |
| D | dscc4.c | 269 #define CCR2 0x10 macro
635 scc_writel(0x00050000, dpriv, dev, CCR2);
878 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2); in dscc4_init_registers()
1063 scc_patchl(0, 0x00050000, dpriv, dev, CCR2); in dscc4_open()
1184 scc_patchl(0x00050000, 0, dpriv, dev, CCR2); in dscc4_close()
1665 scc_writel(0x08050008, dpriv, dev, CCR2); in dscc4_tx_irq()
1803 scc_patchl(RxActivate, 0, dpriv, dev, CCR2); in dscc4_rx_irq()
1856 scc_patchl(0, RxActivate, dpriv, dev, CCR2); in dscc4_rx_irq()
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| /Linux-v4.19/include/linux/ |
| D | omap-dma.h | 153 CPC, CCR2, LCH_CTRL, enumerator
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| /Linux-v4.19/drivers/char/pcmcia/ |
| D | synclink_cs.c | 270 #define CCR2 0x2e macro
2898 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; in mgslpc_set_rate()
2900 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
2967 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
2969 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3002 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3003 write_reg(info, CHA + CCR2, val); in loopback_enable()
3136 write_reg(info, CHA + CCR2, val); in hdlc_mode()
3453 write_reg(info, CHA + CCR2, 0x10); in async_mode()
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| /Linux-v4.19/arch/arm/mach-omap1/ |
| D | dma.c | 78 [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
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| /Linux-v4.19/arch/arm/plat-omap/ |
| D | dma.c | 242 ccr = p->dma_read(CCR2, lch); in omap_set_dma_transfer_params()
246 p->dma_write(ccr, CCR2, lch); in omap_set_dma_transfer_params()
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| /Linux-v4.19/drivers/dma/ti/ |
| D | omap-dma.c | 555 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
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