Searched refs:CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 (Results 1 – 3 of 3) sorted by relevance
50 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 macro60 #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
87 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: in get_pcie_lane_support()
3472 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()3480 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()3487 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()3493 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()3498 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()3502 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()3505 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; in amdgpu_device_get_pcie_info()
