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Searched refs:CACHELINE_BYTES (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/arch/powerpc/lib/
Dstring_32.S16 CACHELINE_BYTES = L1_CACHE_BYTES define
51 addi r6, r6, CACHELINE_BYTES
Dcopy_32.S67 CACHELINE_BYTES = L1_CACHE_BYTES define
128 addi r6,r6,CACHELINE_BYTES
375 addi r3,r3,CACHELINE_BYTES
379 addi r3,r3,CACHELINE_BYTES
Dchecksum_32.S129 CACHELINE_BYTES = L1_CACHE_BYTES define
192 addi r3,r3,CACHELINE_BYTES
196 addi r3,r3,CACHELINE_BYTES
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_ringbuffer.c56 return (head - tail - CACHELINE_BYTES) & (size - 1); in __intel_ring_space()
182 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
216 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
286 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
1155 ring->effective_size -= 2 * CACHELINE_BYTES; in intel_engine_create_ring()
1894 num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); in intel_ring_cacheline_align()
1908 GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); in intel_ring_cacheline_align()
Dintel_lrc.c1482 2 * CACHELINE_BYTES); in gen8_init_indirectctx_bb()
1487 while ((unsigned long)batch % CACHELINE_BYTES) in gen8_init_indirectctx_bb()
1559 + 2 * CACHELINE_BYTES); in gen9_init_indirectctx_bb()
1588 while ((unsigned long)batch % CACHELINE_BYTES) in gen9_init_indirectctx_bb()
1622 while ((unsigned long)batch % CACHELINE_BYTES) in gen10_init_indirectctx_bb()
1716 CACHELINE_BYTES))) { in intel_init_workaround_bb()
2132 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; in gen8_emit_flush_render()
2614 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); in execlists_init_reg_state()
Dintel_ringbuffer.h27 #define CACHELINE_BYTES 64 macro
28 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
876 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid()
/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dscheduler.c519 0, CACHELINE_BYTES, 0); in prepare_shadow_wa_ctx()
531 memset(per_ctx_va, 0, CACHELINE_BYTES); in prepare_shadow_wa_ctx()
1366 CACHELINE_BYTES; in intel_vgpu_create_workload()
Dcmd_parser.c2680 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, in scan_wa_ctx()
2805 roundup(ctx_size + CACHELINE_BYTES, in shadow_indirect_ctx()
2858 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); in combine_wa_ctx()