Searched refs:BXT_P_CR_GT_DISP_PWRON (Results 1 – 5 of 5) sorted by relevance
313 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()374 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()376 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()456 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in bxt_ddi_phy_uninit()458 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in bxt_ddi_phy_uninit()
827 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in intel_dsi_pre_enable()828 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, in intel_dsi_pre_enable()985 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in intel_dsi_post_disable()986 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, in intel_dsi_post_disable()
1620 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) macro
249 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= in intel_vgpu_reset_mmio()
3087 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); in init_bxt_mmio_info()
