Searched refs:BIT_15 (Results 1 – 15 of 15) sorted by relevance
759 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)1009 #define CSRX_FUNCTION BIT_15 /* Function number. */1056 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */1576 #define VCO_ENABLE_DSD BIT_151693 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
103 #define OF_SSTS BIT_15 /* Send SCSI status */476 #define CTIO7_FLAGS_SEND_STATUS BIT_15867 TRC_CMD_DONE = BIT_15,
80 #define BIT_15 0x8000 macro596 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */605 #define NVR_BUSY BIT_15637 #define HSR_RISC_INT BIT_15 /* RISC interrupt */1161 #define MBX_15 BIT_151846 #define PO_DIS_REF_TAG_VALD BIT_153735 #define DT_ISP2031 BIT_15
845 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
3473 mcp->mb[2] = sw_em_1g | BIT_15; in qla2x00_set_serdes_params()3474 mcp->mb[3] = sw_em_2g | BIT_15; in qla2x00_set_serdes_params()3475 mcp->mb[4] = sw_em_4g | BIT_15; in qla2x00_set_serdes_params()5056 mcp->mb[1] = mreq->options | BIT_15 | BIT_6; in qla2x00_echo_test()5397 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); in qla2x00_get_thermal_temp()5821 mcp->mb[10] = BIT_15; in qla2x00_port_logout()
2856 case BIT_15: in qla2x00_gpsc()3279 case BIT_15: in qla24xx_async_gpsc_sp_done()
6798 nv->firmware_options_1 &= cpu_to_le32(~BIT_15); in qlt_24xx_config_nvram_stage1()6902 nv->firmware_options_1 &= cpu_to_le32(~BIT_15); in qlt_81xx_config_nvram_stage1()
191 if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8)) in qla2300_intr_handler()
7043 if (nv->host_p & cpu_to_le32(BIT_15)) { in qla24xx_nvram_config()8103 if (nv->host_p & cpu_to_le32(BIT_15)) { in qla81xx_nvram_config()
41 #define BIT_15 0x8000 macro327 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */979 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
149 #define QLCNIC_MBX_ASYNC_EVENT BIT_15
372 #define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
211 #define BIT_15 0x8000 macro
66 #define QLC_83XX_AUTONEG_ENABLE BIT_15
97 #define BIT_15 0x8000 macro
