Searched refs:BIT9 (Results 1 – 24 of 24) sorted by relevance
217 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */246 #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
617 #define RRSR_36M BIT9795 #define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrup */811 #define IMR_C2HCMD BIT9843 #define PHIMR_CPWM2 BIT9866 #define PHIMR_TXFOVW BIT9894 #define UHIMR_CPWM2 BIT9919 #define UHIMR_TXFOVW BIT9948 #define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */977 #define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */1042 #define RCR_AICV BIT9 /* Accept ICV error packet */
30 #define BIT9 0x00000200 macro
53 #define DYNAMIC_BB_RATE_ADAPTIVE BIT9 /* ODM_BB_RATE_ADAPTIVE */
229 #define IMR_BDOK BIT9250 #define TPPoll_StopBK BIT9380 #define RRSR_36M BIT9
63 #define BIT9 0x00000200 macro
122 #define ALGO_TRACE_SW_EXEC BIT9
2671 u16tmp |= BIT9; in btc8192e2ant_init_hwconfig()
50 #define BIT9 0x00000200 macro
114 #define ALGO_TRACE_SW_EXEC BIT9
399 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */428 #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
160 #define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
70 #define ODM_COMP_RATE_ADAPTIVE BIT9
102 #define ALGO_TRACE_SW_EXEC BIT9
431 ODM_BB_RATE_ADAPTIVE = BIT9,
24 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
27 #define BIT9 0x00000200 macro
28 #define BIT9 0x0200 macro
67 #define BIT9 0x00000200 macro
563 #define MISCSTATUS_DSR_LATCHED BIT9586 #define SICR_DSR_ACTIVE BIT9588 #define SICR_DSR (BIT9|BIT8)1596 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); in mgsl_isr_receive_dma()1705 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()4731 RegValue |= BIT9; in usc_set_sdlc_mode()4733 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()4806 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()4808 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()4977 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()[all …]
416 #define IRQ_RXIDLE BIT9 /* HDLC */417 #define IRQ_RXBREAK BIT9 /* async */4132 val |= BIT9; in async_mode()4172 val |= BIT9; in async_mode()4295 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()4296 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()4368 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()4369 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()5012 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
389 #define RRSR_36M BIT9
707 #define LPFC_SLI4_INTR9 BIT9
296 #define IRQ_TXREPEAT BIT9 // tx message repeat
