1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/rbtree.h>
36 #include <linux/hashtable.h>
37 #include <linux/dma-fence.h>
38
39 #include <drm/ttm/ttm_bo_api.h>
40 #include <drm/ttm/ttm_bo_driver.h>
41 #include <drm/ttm/ttm_placement.h>
42 #include <drm/ttm/ttm_module.h>
43 #include <drm/ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48 #include <drm/gpu_scheduler.h>
49
50 #include <kgd_kfd_interface.h>
51 #include "dm_pp_interface.h"
52 #include "kgd_pp_interface.h"
53
54 #include "amd_shared.h"
55 #include "amdgpu_mode.h"
56 #include "amdgpu_ih.h"
57 #include "amdgpu_irq.h"
58 #include "amdgpu_ucode.h"
59 #include "amdgpu_ttm.h"
60 #include "amdgpu_psp.h"
61 #include "amdgpu_gds.h"
62 #include "amdgpu_sync.h"
63 #include "amdgpu_ring.h"
64 #include "amdgpu_vm.h"
65 #include "amdgpu_dpm.h"
66 #include "amdgpu_acp.h"
67 #include "amdgpu_uvd.h"
68 #include "amdgpu_vce.h"
69 #include "amdgpu_vcn.h"
70 #include "amdgpu_mn.h"
71 #include "amdgpu_gmc.h"
72 #include "amdgpu_dm.h"
73 #include "amdgpu_virt.h"
74 #include "amdgpu_gart.h"
75 #include "amdgpu_debugfs.h"
76 #include "amdgpu_job.h"
77 #include "amdgpu_bo_list.h"
78
79 /*
80 * Modules parameters.
81 */
82 extern int amdgpu_modeset;
83 extern int amdgpu_vram_limit;
84 extern int amdgpu_vis_vram_limit;
85 extern int amdgpu_gart_size;
86 extern int amdgpu_gtt_size;
87 extern int amdgpu_moverate;
88 extern int amdgpu_benchmarking;
89 extern int amdgpu_testing;
90 extern int amdgpu_audio;
91 extern int amdgpu_disp_priority;
92 extern int amdgpu_hw_i2c;
93 extern int amdgpu_pcie_gen2;
94 extern int amdgpu_msi;
95 extern int amdgpu_lockup_timeout;
96 extern int amdgpu_dpm;
97 extern int amdgpu_fw_load_type;
98 extern int amdgpu_aspm;
99 extern int amdgpu_runtime_pm;
100 extern uint amdgpu_ip_block_mask;
101 extern int amdgpu_bapm;
102 extern int amdgpu_deep_color;
103 extern int amdgpu_vm_size;
104 extern int amdgpu_vm_block_size;
105 extern int amdgpu_vm_fragment_size;
106 extern int amdgpu_vm_fault_stop;
107 extern int amdgpu_vm_debug;
108 extern int amdgpu_vm_update_mode;
109 extern int amdgpu_dc;
110 extern int amdgpu_sched_jobs;
111 extern int amdgpu_sched_hw_submission;
112 extern uint amdgpu_pcie_gen_cap;
113 extern uint amdgpu_pcie_lane_cap;
114 extern uint amdgpu_cg_mask;
115 extern uint amdgpu_pg_mask;
116 extern uint amdgpu_sdma_phase_quantum;
117 extern char *amdgpu_disable_cu;
118 extern char *amdgpu_virtual_display;
119 extern uint amdgpu_pp_feature_mask;
120 extern int amdgpu_vram_page_split;
121 extern int amdgpu_ngg;
122 extern int amdgpu_prim_buf_per_se;
123 extern int amdgpu_pos_buf_per_se;
124 extern int amdgpu_cntl_sb_buf_per_se;
125 extern int amdgpu_param_buf_per_se;
126 extern int amdgpu_job_hang_limit;
127 extern int amdgpu_lbpw;
128 extern int amdgpu_compute_multipipe;
129 extern int amdgpu_gpu_recovery;
130 extern int amdgpu_emu_mode;
131 extern uint amdgpu_smu_memory_pool_size;
132
133 #ifdef CONFIG_DRM_AMDGPU_SI
134 extern int amdgpu_si_support;
135 #endif
136 #ifdef CONFIG_DRM_AMDGPU_CIK
137 extern int amdgpu_cik_support;
138 #endif
139
140 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
141 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
142 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
143 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
144 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
145 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
146 #define AMDGPU_IB_POOL_SIZE 16
147 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
148 #define AMDGPUFB_CONN_LIMIT 4
149 #define AMDGPU_BIOS_NUM_SCRATCH 16
150
151 /* max number of IP instances */
152 #define AMDGPU_MAX_SDMA_INSTANCES 2
153
154 /* hard reset data */
155 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
156
157 /* reset flags */
158 #define AMDGPU_RESET_GFX (1 << 0)
159 #define AMDGPU_RESET_COMPUTE (1 << 1)
160 #define AMDGPU_RESET_DMA (1 << 2)
161 #define AMDGPU_RESET_CP (1 << 3)
162 #define AMDGPU_RESET_GRBM (1 << 4)
163 #define AMDGPU_RESET_DMA1 (1 << 5)
164 #define AMDGPU_RESET_RLC (1 << 6)
165 #define AMDGPU_RESET_SEM (1 << 7)
166 #define AMDGPU_RESET_IH (1 << 8)
167 #define AMDGPU_RESET_VMC (1 << 9)
168 #define AMDGPU_RESET_MC (1 << 10)
169 #define AMDGPU_RESET_DISPLAY (1 << 11)
170 #define AMDGPU_RESET_UVD (1 << 12)
171 #define AMDGPU_RESET_VCE (1 << 13)
172 #define AMDGPU_RESET_VCE1 (1 << 14)
173
174 /* GFX current status */
175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180
181 /* max cursor sizes (in pixels) */
182 #define CIK_CURSOR_WIDTH 128
183 #define CIK_CURSOR_HEIGHT 128
184
185 struct amdgpu_device;
186 struct amdgpu_ib;
187 struct amdgpu_cs_parser;
188 struct amdgpu_job;
189 struct amdgpu_irq_src;
190 struct amdgpu_fpriv;
191 struct amdgpu_bo_va_mapping;
192 struct amdgpu_atif;
193
194 enum amdgpu_cp_irq {
195 AMDGPU_CP_IRQ_GFX_EOP = 0,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
204
205 AMDGPU_CP_IRQ_LAST
206 };
207
208 enum amdgpu_sdma_irq {
209 AMDGPU_SDMA_IRQ_TRAP0 = 0,
210 AMDGPU_SDMA_IRQ_TRAP1,
211
212 AMDGPU_SDMA_IRQ_LAST
213 };
214
215 enum amdgpu_thermal_irq {
216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
218
219 AMDGPU_THERMAL_IRQ_LAST
220 };
221
222 enum amdgpu_kiq_irq {
223 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
224 AMDGPU_CP_KIQ_IRQ_LAST
225 };
226
227 int amdgpu_device_ip_set_clockgating_state(void *dev,
228 enum amd_ip_block_type block_type,
229 enum amd_clockgating_state state);
230 int amdgpu_device_ip_set_powergating_state(void *dev,
231 enum amd_ip_block_type block_type,
232 enum amd_powergating_state state);
233 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
234 u32 *flags);
235 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
236 enum amd_ip_block_type block_type);
237 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
238 enum amd_ip_block_type block_type);
239
240 #define AMDGPU_MAX_IP_NUM 16
241
242 struct amdgpu_ip_block_status {
243 bool valid;
244 bool sw;
245 bool hw;
246 bool late_initialized;
247 bool hang;
248 };
249
250 struct amdgpu_ip_block_version {
251 const enum amd_ip_block_type type;
252 const u32 major;
253 const u32 minor;
254 const u32 rev;
255 const struct amd_ip_funcs *funcs;
256 };
257
258 struct amdgpu_ip_block {
259 struct amdgpu_ip_block_status status;
260 const struct amdgpu_ip_block_version *version;
261 };
262
263 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
264 enum amd_ip_block_type type,
265 u32 major, u32 minor);
266
267 struct amdgpu_ip_block *
268 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
269 enum amd_ip_block_type type);
270
271 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
272 const struct amdgpu_ip_block_version *ip_block_version);
273
274 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
275 struct amdgpu_buffer_funcs {
276 /* maximum bytes in a single operation */
277 uint32_t copy_max_bytes;
278
279 /* number of dw to reserve per operation */
280 unsigned copy_num_dw;
281
282 /* used for buffer migration */
283 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
284 /* src addr in bytes */
285 uint64_t src_offset,
286 /* dst addr in bytes */
287 uint64_t dst_offset,
288 /* number of byte to transfer */
289 uint32_t byte_count);
290
291 /* maximum bytes in a single operation */
292 uint32_t fill_max_bytes;
293
294 /* number of dw to reserve per operation */
295 unsigned fill_num_dw;
296
297 /* used for buffer clearing */
298 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
299 /* value to write to memory */
300 uint32_t src_data,
301 /* dst addr in bytes */
302 uint64_t dst_offset,
303 /* number of byte to fill */
304 uint32_t byte_count);
305 };
306
307 /* provided by hw blocks that can write ptes, e.g., sdma */
308 struct amdgpu_vm_pte_funcs {
309 /* number of dw to reserve per operation */
310 unsigned copy_pte_num_dw;
311
312 /* copy pte entries from GART */
313 void (*copy_pte)(struct amdgpu_ib *ib,
314 uint64_t pe, uint64_t src,
315 unsigned count);
316
317 /* write pte one entry at a time with addr mapping */
318 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
319 uint64_t value, unsigned count,
320 uint32_t incr);
321 /* for linear pte/pde updates without addr mapping */
322 void (*set_pte_pde)(struct amdgpu_ib *ib,
323 uint64_t pe,
324 uint64_t addr, unsigned count,
325 uint32_t incr, uint64_t flags);
326 };
327
328 /* provided by the ih block */
329 struct amdgpu_ih_funcs {
330 /* ring read/write ptr handling, called from interrupt context */
331 u32 (*get_wptr)(struct amdgpu_device *adev);
332 bool (*prescreen_iv)(struct amdgpu_device *adev);
333 void (*decode_iv)(struct amdgpu_device *adev,
334 struct amdgpu_iv_entry *entry);
335 void (*set_rptr)(struct amdgpu_device *adev);
336 };
337
338 /*
339 * BIOS.
340 */
341 bool amdgpu_get_bios(struct amdgpu_device *adev);
342 bool amdgpu_read_bios(struct amdgpu_device *adev);
343
344 /*
345 * Clocks
346 */
347
348 #define AMDGPU_MAX_PPLL 3
349
350 struct amdgpu_clock {
351 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
352 struct amdgpu_pll spll;
353 struct amdgpu_pll mpll;
354 /* 10 Khz units */
355 uint32_t default_mclk;
356 uint32_t default_sclk;
357 uint32_t default_dispclk;
358 uint32_t current_dispclk;
359 uint32_t dp_extclk;
360 uint32_t max_pixel_clock;
361 };
362
363 /*
364 * GEM.
365 */
366
367 #define AMDGPU_GEM_DOMAIN_MAX 0x3
368 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
369
370 void amdgpu_gem_object_free(struct drm_gem_object *obj);
371 int amdgpu_gem_object_open(struct drm_gem_object *obj,
372 struct drm_file *file_priv);
373 void amdgpu_gem_object_close(struct drm_gem_object *obj,
374 struct drm_file *file_priv);
375 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
376 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
377 struct drm_gem_object *
378 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
379 struct dma_buf_attachment *attach,
380 struct sg_table *sg);
381 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
382 struct drm_gem_object *gobj,
383 int flags);
384 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
385 struct dma_buf *dma_buf);
386 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
387 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
388 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
389 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
390
391 /* sub-allocation manager, it has to be protected by another lock.
392 * By conception this is an helper for other part of the driver
393 * like the indirect buffer or semaphore, which both have their
394 * locking.
395 *
396 * Principe is simple, we keep a list of sub allocation in offset
397 * order (first entry has offset == 0, last entry has the highest
398 * offset).
399 *
400 * When allocating new object we first check if there is room at
401 * the end total_size - (last_object_offset + last_object_size) >=
402 * alloc_size. If so we allocate new object there.
403 *
404 * When there is not enough room at the end, we start waiting for
405 * each sub object until we reach object_offset+object_size >=
406 * alloc_size, this object then become the sub object we return.
407 *
408 * Alignment can't be bigger than page size.
409 *
410 * Hole are not considered for allocation to keep things simple.
411 * Assumption is that there won't be hole (all object on same
412 * alignment).
413 */
414
415 #define AMDGPU_SA_NUM_FENCE_LISTS 32
416
417 struct amdgpu_sa_manager {
418 wait_queue_head_t wq;
419 struct amdgpu_bo *bo;
420 struct list_head *hole;
421 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
422 struct list_head olist;
423 unsigned size;
424 uint64_t gpu_addr;
425 void *cpu_ptr;
426 uint32_t domain;
427 uint32_t align;
428 };
429
430 /* sub-allocation buffer */
431 struct amdgpu_sa_bo {
432 struct list_head olist;
433 struct list_head flist;
434 struct amdgpu_sa_manager *manager;
435 unsigned soffset;
436 unsigned eoffset;
437 struct dma_fence *fence;
438 };
439
440 /*
441 * GEM objects.
442 */
443 void amdgpu_gem_force_release(struct amdgpu_device *adev);
444 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
445 int alignment, u32 initial_domain,
446 u64 flags, enum ttm_bo_type type,
447 struct reservation_object *resv,
448 struct drm_gem_object **obj);
449
450 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
451 struct drm_device *dev,
452 struct drm_mode_create_dumb *args);
453 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
454 struct drm_device *dev,
455 uint32_t handle, uint64_t *offset_p);
456 int amdgpu_fence_slab_init(void);
457 void amdgpu_fence_slab_fini(void);
458
459 /*
460 * GPU doorbell structures, functions & helpers
461 */
462 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
463 {
464 AMDGPU_DOORBELL_KIQ = 0x000,
465 AMDGPU_DOORBELL_HIQ = 0x001,
466 AMDGPU_DOORBELL_DIQ = 0x002,
467 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
468 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
469 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
470 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
471 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
472 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
473 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
474 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
475 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
476 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
477 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
478 AMDGPU_DOORBELL_IH = 0x1E8,
479 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
480 AMDGPU_DOORBELL_INVALID = 0xFFFF
481 } AMDGPU_DOORBELL_ASSIGNMENT;
482
483 struct amdgpu_doorbell {
484 /* doorbell mmio */
485 resource_size_t base;
486 resource_size_t size;
487 u32 __iomem *ptr;
488 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
489 };
490
491 /*
492 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
493 */
494 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
495 {
496 /*
497 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
498 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
499 * Compute related doorbells are allocated from 0x00 to 0x8a
500 */
501
502
503 /* kernel scheduling */
504 AMDGPU_DOORBELL64_KIQ = 0x00,
505
506 /* HSA interface queue and debug queue */
507 AMDGPU_DOORBELL64_HIQ = 0x01,
508 AMDGPU_DOORBELL64_DIQ = 0x02,
509
510 /* Compute engines */
511 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
512 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
513 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
514 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
515 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
516 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
517 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
518 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
519
520 /* User queue doorbell range (128 doorbells) */
521 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
522 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
523
524 /* Graphics engine */
525 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
526
527 /*
528 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
529 * Graphics voltage island aperture 1
530 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
531 */
532
533 /* sDMA engines */
534 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
535 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
536 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
537 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
538
539 /* Interrupt handler */
540 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
541 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
542 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
543
544 /* VCN engine use 32 bits doorbell */
545 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
546 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
547 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
548 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
549
550 /* overlap the doorbell assignment with VCN as they are mutually exclusive
551 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
552 */
553 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
554 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
555 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
556 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
557
558 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
559 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
560 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
561 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
562
563 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
564 AMDGPU_DOORBELL64_INVALID = 0xFFFF
565 } AMDGPU_DOORBELL64_ASSIGNMENT;
566
567 /*
568 * IRQS.
569 */
570
571 struct amdgpu_flip_work {
572 struct delayed_work flip_work;
573 struct work_struct unpin_work;
574 struct amdgpu_device *adev;
575 int crtc_id;
576 u32 target_vblank;
577 uint64_t base;
578 struct drm_pending_vblank_event *event;
579 struct amdgpu_bo *old_abo;
580 struct dma_fence *excl;
581 unsigned shared_count;
582 struct dma_fence **shared;
583 struct dma_fence_cb cb;
584 bool async;
585 };
586
587
588 /*
589 * CP & rings.
590 */
591
592 struct amdgpu_ib {
593 struct amdgpu_sa_bo *sa_bo;
594 uint32_t length_dw;
595 uint64_t gpu_addr;
596 uint32_t *ptr;
597 uint32_t flags;
598 };
599
600 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
601
602 /*
603 * Queue manager
604 */
605 struct amdgpu_queue_mapper {
606 int hw_ip;
607 struct mutex lock;
608 /* protected by lock */
609 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
610 };
611
612 struct amdgpu_queue_mgr {
613 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
614 };
615
616 int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
617 struct amdgpu_queue_mgr *mgr);
618 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
619 struct amdgpu_queue_mgr *mgr);
620 int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
621 struct amdgpu_queue_mgr *mgr,
622 u32 hw_ip, u32 instance, u32 ring,
623 struct amdgpu_ring **out_ring);
624
625 /*
626 * context related structures
627 */
628
629 struct amdgpu_ctx_ring {
630 uint64_t sequence;
631 struct dma_fence **fences;
632 struct drm_sched_entity entity;
633 };
634
635 struct amdgpu_ctx {
636 struct kref refcount;
637 struct amdgpu_device *adev;
638 struct amdgpu_queue_mgr queue_mgr;
639 unsigned reset_counter;
640 unsigned reset_counter_query;
641 uint32_t vram_lost_counter;
642 spinlock_t ring_lock;
643 struct dma_fence **fences;
644 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
645 bool preamble_presented;
646 enum drm_sched_priority init_priority;
647 enum drm_sched_priority override_priority;
648 struct mutex lock;
649 atomic_t guilty;
650 };
651
652 struct amdgpu_ctx_mgr {
653 struct amdgpu_device *adev;
654 struct mutex lock;
655 /* protected by lock */
656 struct idr ctx_handles;
657 };
658
659 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
660 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
661
662 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
663 struct dma_fence *fence, uint64_t *seq);
664 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
665 struct amdgpu_ring *ring, uint64_t seq);
666 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
667 enum drm_sched_priority priority);
668
669 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
670 struct drm_file *filp);
671
672 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
673
674 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
675 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
676 void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr);
677 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
678
679
680 /*
681 * file private structure
682 */
683
684 struct amdgpu_fpriv {
685 struct amdgpu_vm vm;
686 struct amdgpu_bo_va *prt_va;
687 struct amdgpu_bo_va *csa_va;
688 struct mutex bo_list_lock;
689 struct idr bo_list_handles;
690 struct amdgpu_ctx_mgr ctx_mgr;
691 };
692
693 /*
694 * GFX stuff
695 */
696 #include "clearstate_defs.h"
697
698 struct amdgpu_rlc_funcs {
699 void (*enter_safe_mode)(struct amdgpu_device *adev);
700 void (*exit_safe_mode)(struct amdgpu_device *adev);
701 };
702
703 struct amdgpu_rlc {
704 /* for power gating */
705 struct amdgpu_bo *save_restore_obj;
706 uint64_t save_restore_gpu_addr;
707 volatile uint32_t *sr_ptr;
708 const u32 *reg_list;
709 u32 reg_list_size;
710 /* for clear state */
711 struct amdgpu_bo *clear_state_obj;
712 uint64_t clear_state_gpu_addr;
713 volatile uint32_t *cs_ptr;
714 const struct cs_section_def *cs_data;
715 u32 clear_state_size;
716 /* for cp tables */
717 struct amdgpu_bo *cp_table_obj;
718 uint64_t cp_table_gpu_addr;
719 volatile uint32_t *cp_table_ptr;
720 u32 cp_table_size;
721
722 /* safe mode for updating CG/PG state */
723 bool in_safe_mode;
724 const struct amdgpu_rlc_funcs *funcs;
725
726 /* for firmware data */
727 u32 save_and_restore_offset;
728 u32 clear_state_descriptor_offset;
729 u32 avail_scratch_ram_locations;
730 u32 reg_restore_list_size;
731 u32 reg_list_format_start;
732 u32 reg_list_format_separate_start;
733 u32 starting_offsets_start;
734 u32 reg_list_format_size_bytes;
735 u32 reg_list_size_bytes;
736 u32 reg_list_format_direct_reg_list_length;
737 u32 save_restore_list_cntl_size_bytes;
738 u32 save_restore_list_gpm_size_bytes;
739 u32 save_restore_list_srm_size_bytes;
740
741 u32 *register_list_format;
742 u32 *register_restore;
743 u8 *save_restore_list_cntl;
744 u8 *save_restore_list_gpm;
745 u8 *save_restore_list_srm;
746
747 bool is_rlc_v2_1;
748 };
749
750 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
751
752 struct amdgpu_mec {
753 struct amdgpu_bo *hpd_eop_obj;
754 u64 hpd_eop_gpu_addr;
755 struct amdgpu_bo *mec_fw_obj;
756 u64 mec_fw_gpu_addr;
757 u32 num_mec;
758 u32 num_pipe_per_mec;
759 u32 num_queue_per_pipe;
760 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
761
762 /* These are the resources for which amdgpu takes ownership */
763 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
764 };
765
766 struct amdgpu_kiq {
767 u64 eop_gpu_addr;
768 struct amdgpu_bo *eop_obj;
769 spinlock_t ring_lock;
770 struct amdgpu_ring ring;
771 struct amdgpu_irq_src irq;
772 };
773
774 /*
775 * GPU scratch registers structures, functions & helpers
776 */
777 struct amdgpu_scratch {
778 unsigned num_reg;
779 uint32_t reg_base;
780 uint32_t free_mask;
781 };
782
783 /*
784 * GFX configurations
785 */
786 #define AMDGPU_GFX_MAX_SE 4
787 #define AMDGPU_GFX_MAX_SH_PER_SE 2
788
789 struct amdgpu_rb_config {
790 uint32_t rb_backend_disable;
791 uint32_t user_rb_backend_disable;
792 uint32_t raster_config;
793 uint32_t raster_config_1;
794 };
795
796 struct gb_addr_config {
797 uint16_t pipe_interleave_size;
798 uint8_t num_pipes;
799 uint8_t max_compress_frags;
800 uint8_t num_banks;
801 uint8_t num_se;
802 uint8_t num_rb_per_se;
803 };
804
805 struct amdgpu_gfx_config {
806 unsigned max_shader_engines;
807 unsigned max_tile_pipes;
808 unsigned max_cu_per_sh;
809 unsigned max_sh_per_se;
810 unsigned max_backends_per_se;
811 unsigned max_texture_channel_caches;
812 unsigned max_gprs;
813 unsigned max_gs_threads;
814 unsigned max_hw_contexts;
815 unsigned sc_prim_fifo_size_frontend;
816 unsigned sc_prim_fifo_size_backend;
817 unsigned sc_hiz_tile_fifo_size;
818 unsigned sc_earlyz_tile_fifo_size;
819
820 unsigned num_tile_pipes;
821 unsigned backend_enable_mask;
822 unsigned mem_max_burst_length_bytes;
823 unsigned mem_row_size_in_kb;
824 unsigned shader_engine_tile_size;
825 unsigned num_gpus;
826 unsigned multi_gpu_tile_size;
827 unsigned mc_arb_ramcfg;
828 unsigned gb_addr_config;
829 unsigned num_rbs;
830 unsigned gs_vgt_table_depth;
831 unsigned gs_prim_buffer_depth;
832
833 uint32_t tile_mode_array[32];
834 uint32_t macrotile_mode_array[16];
835
836 struct gb_addr_config gb_addr_config_fields;
837 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
838
839 /* gfx configure feature */
840 uint32_t double_offchip_lds_buf;
841 /* cached value of DB_DEBUG2 */
842 uint32_t db_debug2;
843 };
844
845 struct amdgpu_cu_info {
846 uint32_t simd_per_cu;
847 uint32_t max_waves_per_simd;
848 uint32_t wave_front_size;
849 uint32_t max_scratch_slots_per_cu;
850 uint32_t lds_size;
851
852 /* total active CU number */
853 uint32_t number;
854 uint32_t ao_cu_mask;
855 uint32_t ao_cu_bitmap[4][4];
856 uint32_t bitmap[4][4];
857 };
858
859 struct amdgpu_gfx_funcs {
860 /* get the gpu clock counter */
861 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
862 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
863 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
864 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
865 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
866 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue);
867 };
868
869 struct amdgpu_ngg_buf {
870 struct amdgpu_bo *bo;
871 uint64_t gpu_addr;
872 uint32_t size;
873 uint32_t bo_size;
874 };
875
876 enum {
877 NGG_PRIM = 0,
878 NGG_POS,
879 NGG_CNTL,
880 NGG_PARAM,
881 NGG_BUF_MAX
882 };
883
884 struct amdgpu_ngg {
885 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
886 uint32_t gds_reserve_addr;
887 uint32_t gds_reserve_size;
888 bool init;
889 };
890
891 struct sq_work {
892 struct work_struct work;
893 unsigned ih_data;
894 };
895
896 struct amdgpu_gfx {
897 struct mutex gpu_clock_mutex;
898 struct amdgpu_gfx_config config;
899 struct amdgpu_rlc rlc;
900 struct amdgpu_mec mec;
901 struct amdgpu_kiq kiq;
902 struct amdgpu_scratch scratch;
903 const struct firmware *me_fw; /* ME firmware */
904 uint32_t me_fw_version;
905 const struct firmware *pfp_fw; /* PFP firmware */
906 uint32_t pfp_fw_version;
907 const struct firmware *ce_fw; /* CE firmware */
908 uint32_t ce_fw_version;
909 const struct firmware *rlc_fw; /* RLC firmware */
910 uint32_t rlc_fw_version;
911 const struct firmware *mec_fw; /* MEC firmware */
912 uint32_t mec_fw_version;
913 const struct firmware *mec2_fw; /* MEC2 firmware */
914 uint32_t mec2_fw_version;
915 uint32_t me_feature_version;
916 uint32_t ce_feature_version;
917 uint32_t pfp_feature_version;
918 uint32_t rlc_feature_version;
919 uint32_t rlc_srlc_fw_version;
920 uint32_t rlc_srlc_feature_version;
921 uint32_t rlc_srlg_fw_version;
922 uint32_t rlc_srlg_feature_version;
923 uint32_t rlc_srls_fw_version;
924 uint32_t rlc_srls_feature_version;
925 uint32_t mec_feature_version;
926 uint32_t mec2_feature_version;
927 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
928 unsigned num_gfx_rings;
929 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
930 unsigned num_compute_rings;
931 struct amdgpu_irq_src eop_irq;
932 struct amdgpu_irq_src priv_reg_irq;
933 struct amdgpu_irq_src priv_inst_irq;
934 struct amdgpu_irq_src cp_ecc_error_irq;
935 struct amdgpu_irq_src sq_irq;
936 struct sq_work sq_work;
937
938 /* gfx status */
939 uint32_t gfx_current_status;
940 /* ce ram size*/
941 unsigned ce_ram_size;
942 struct amdgpu_cu_info cu_info;
943 const struct amdgpu_gfx_funcs *funcs;
944
945 /* reset mask */
946 uint32_t grbm_soft_reset;
947 uint32_t srbm_soft_reset;
948 /* s3/s4 mask */
949 bool in_suspend;
950 /* NGG */
951 struct amdgpu_ngg ngg;
952
953 /* pipe reservation */
954 struct mutex pipe_reserve_mutex;
955 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
956 };
957
958 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
959 unsigned size, struct amdgpu_ib *ib);
960 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
961 struct dma_fence *f);
962 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
963 struct amdgpu_ib *ibs, struct amdgpu_job *job,
964 struct dma_fence **f);
965 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
966 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
967 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
968
969 /*
970 * CS.
971 */
972 struct amdgpu_cs_chunk {
973 uint32_t chunk_id;
974 uint32_t length_dw;
975 void *kdata;
976 };
977
978 struct amdgpu_cs_parser {
979 struct amdgpu_device *adev;
980 struct drm_file *filp;
981 struct amdgpu_ctx *ctx;
982
983 /* chunks */
984 unsigned nchunks;
985 struct amdgpu_cs_chunk *chunks;
986
987 /* scheduler job object */
988 struct amdgpu_job *job;
989 struct amdgpu_ring *ring;
990
991 /* buffer objects */
992 struct ww_acquire_ctx ticket;
993 struct amdgpu_bo_list *bo_list;
994 struct amdgpu_mn *mn;
995 struct amdgpu_bo_list_entry vm_pd;
996 struct list_head validated;
997 struct dma_fence *fence;
998 uint64_t bytes_moved_threshold;
999 uint64_t bytes_moved_vis_threshold;
1000 uint64_t bytes_moved;
1001 uint64_t bytes_moved_vis;
1002 struct amdgpu_bo_list_entry *evictable;
1003
1004 /* user fence */
1005 struct amdgpu_bo_list_entry uf_entry;
1006
1007 unsigned num_post_dep_syncobjs;
1008 struct drm_syncobj **post_dep_syncobjs;
1009 };
1010
amdgpu_get_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx)1011 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1012 uint32_t ib_idx, int idx)
1013 {
1014 return p->job->ibs[ib_idx].ptr[idx];
1015 }
1016
amdgpu_set_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx,uint32_t value)1017 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1018 uint32_t ib_idx, int idx,
1019 uint32_t value)
1020 {
1021 p->job->ibs[ib_idx].ptr[idx] = value;
1022 }
1023
1024 /*
1025 * Writeback
1026 */
1027 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
1028
1029 struct amdgpu_wb {
1030 struct amdgpu_bo *wb_obj;
1031 volatile uint32_t *wb;
1032 uint64_t gpu_addr;
1033 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1034 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1035 };
1036
1037 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
1038 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
1039
1040 /*
1041 * SDMA
1042 */
1043 struct amdgpu_sdma_instance {
1044 /* SDMA firmware */
1045 const struct firmware *fw;
1046 uint32_t fw_version;
1047 uint32_t feature_version;
1048
1049 struct amdgpu_ring ring;
1050 bool burst_nop;
1051 };
1052
1053 struct amdgpu_sdma {
1054 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1055 #ifdef CONFIG_DRM_AMDGPU_SI
1056 //SI DMA has a difference trap irq number for the second engine
1057 struct amdgpu_irq_src trap_irq_1;
1058 #endif
1059 struct amdgpu_irq_src trap_irq;
1060 struct amdgpu_irq_src illegal_inst_irq;
1061 int num_instances;
1062 uint32_t srbm_soft_reset;
1063 };
1064
1065 /*
1066 * Firmware
1067 */
1068 enum amdgpu_firmware_load_type {
1069 AMDGPU_FW_LOAD_DIRECT = 0,
1070 AMDGPU_FW_LOAD_SMU,
1071 AMDGPU_FW_LOAD_PSP,
1072 };
1073
1074 struct amdgpu_firmware {
1075 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1076 enum amdgpu_firmware_load_type load_type;
1077 struct amdgpu_bo *fw_buf;
1078 unsigned int fw_size;
1079 unsigned int max_ucodes;
1080 /* firmwares are loaded by psp instead of smu from vega10 */
1081 const struct amdgpu_psp_funcs *funcs;
1082 struct amdgpu_bo *rbuf;
1083 struct mutex mutex;
1084
1085 /* gpu info firmware data pointer */
1086 const struct firmware *gpu_info_fw;
1087
1088 void *fw_buf_ptr;
1089 uint64_t fw_buf_mc;
1090 };
1091
1092 /*
1093 * Benchmarking
1094 */
1095 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1096
1097
1098 /*
1099 * Testing
1100 */
1101 void amdgpu_test_moves(struct amdgpu_device *adev);
1102
1103
1104 /*
1105 * amdgpu smumgr functions
1106 */
1107 struct amdgpu_smumgr_funcs {
1108 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1109 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1110 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1111 };
1112
1113 /*
1114 * amdgpu smumgr
1115 */
1116 struct amdgpu_smumgr {
1117 struct amdgpu_bo *toc_buf;
1118 struct amdgpu_bo *smu_buf;
1119 /* asic priv smu data */
1120 void *priv;
1121 spinlock_t smu_lock;
1122 /* smumgr functions */
1123 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1124 /* ucode loading complete flag */
1125 uint32_t fw_flags;
1126 };
1127
1128 /*
1129 * ASIC specific register table accessible by UMD
1130 */
1131 struct amdgpu_allowed_register_entry {
1132 uint32_t reg_offset;
1133 bool grbm_indexed;
1134 };
1135
1136 /*
1137 * ASIC specific functions.
1138 */
1139 struct amdgpu_asic_funcs {
1140 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1141 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1142 u8 *bios, u32 length_bytes);
1143 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1144 u32 sh_num, u32 reg_offset, u32 *value);
1145 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1146 int (*reset)(struct amdgpu_device *adev);
1147 /* get the reference clock */
1148 u32 (*get_xclk)(struct amdgpu_device *adev);
1149 /* MM block clocks */
1150 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1151 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1152 /* static power management */
1153 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1154 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1155 /* get config memsize register */
1156 u32 (*get_config_memsize)(struct amdgpu_device *adev);
1157 /* flush hdp write queue */
1158 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
1159 /* invalidate hdp read cache */
1160 void (*invalidate_hdp)(struct amdgpu_device *adev,
1161 struct amdgpu_ring *ring);
1162 /* check if the asic needs a full reset of if soft reset will work */
1163 bool (*need_full_reset)(struct amdgpu_device *adev);
1164 };
1165
1166 /*
1167 * IOCTL.
1168 */
1169 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1170 struct drm_file *filp);
1171 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1172 struct drm_file *filp);
1173
1174 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1175 struct drm_file *filp);
1176 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1177 struct drm_file *filp);
1178 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *filp);
1180 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1181 struct drm_file *filp);
1182 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1183 struct drm_file *filp);
1184 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1185 struct drm_file *filp);
1186 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1187 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *filp);
1189 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1190 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1191 struct drm_file *filp);
1192
1193 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1194 struct drm_file *filp);
1195
1196 /* VRAM scratch page for HDP bug, default vram page */
1197 struct amdgpu_vram_scratch {
1198 struct amdgpu_bo *robj;
1199 volatile uint32_t *ptr;
1200 u64 gpu_addr;
1201 };
1202
1203 /*
1204 * ACPI
1205 */
1206 struct amdgpu_atcs_functions {
1207 bool get_ext_state;
1208 bool pcie_perf_req;
1209 bool pcie_dev_rdy;
1210 bool pcie_bus_width;
1211 };
1212
1213 struct amdgpu_atcs {
1214 struct amdgpu_atcs_functions functions;
1215 };
1216
1217 /*
1218 * Firmware VRAM reservation
1219 */
1220 struct amdgpu_fw_vram_usage {
1221 u64 start_offset;
1222 u64 size;
1223 struct amdgpu_bo *reserved_bo;
1224 void *va;
1225 };
1226
1227 /*
1228 * CGS
1229 */
1230 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1231 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1232
1233 /*
1234 * Core structure, functions and helpers.
1235 */
1236 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1237 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1238
1239 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1240 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1241
1242
1243 /*
1244 * amdgpu nbio functions
1245 *
1246 */
1247 struct nbio_hdp_flush_reg {
1248 u32 ref_and_mask_cp0;
1249 u32 ref_and_mask_cp1;
1250 u32 ref_and_mask_cp2;
1251 u32 ref_and_mask_cp3;
1252 u32 ref_and_mask_cp4;
1253 u32 ref_and_mask_cp5;
1254 u32 ref_and_mask_cp6;
1255 u32 ref_and_mask_cp7;
1256 u32 ref_and_mask_cp8;
1257 u32 ref_and_mask_cp9;
1258 u32 ref_and_mask_sdma0;
1259 u32 ref_and_mask_sdma1;
1260 };
1261
1262 struct amdgpu_nbio_funcs {
1263 const struct nbio_hdp_flush_reg *hdp_flush_reg;
1264 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
1265 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
1266 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
1267 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
1268 u32 (*get_rev_id)(struct amdgpu_device *adev);
1269 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
1270 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
1271 u32 (*get_memsize)(struct amdgpu_device *adev);
1272 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
1273 bool use_doorbell, int doorbell_index);
1274 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
1275 bool enable);
1276 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
1277 bool enable);
1278 void (*ih_doorbell_range)(struct amdgpu_device *adev,
1279 bool use_doorbell, int doorbell_index);
1280 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
1281 bool enable);
1282 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
1283 bool enable);
1284 void (*get_clockgating_state)(struct amdgpu_device *adev,
1285 u32 *flags);
1286 void (*ih_control)(struct amdgpu_device *adev);
1287 void (*init_registers)(struct amdgpu_device *adev);
1288 void (*detect_hw_virt)(struct amdgpu_device *adev);
1289 };
1290
1291 struct amdgpu_df_funcs {
1292 void (*init)(struct amdgpu_device *adev);
1293 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
1294 bool enable);
1295 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
1296 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
1297 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
1298 bool enable);
1299 void (*get_clockgating_state)(struct amdgpu_device *adev,
1300 u32 *flags);
1301 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
1302 bool enable);
1303 };
1304 /* Define the HW IP blocks will be used in driver , add more if necessary */
1305 enum amd_hw_ip_block_type {
1306 GC_HWIP = 1,
1307 HDP_HWIP,
1308 SDMA0_HWIP,
1309 SDMA1_HWIP,
1310 MMHUB_HWIP,
1311 ATHUB_HWIP,
1312 NBIO_HWIP,
1313 MP0_HWIP,
1314 MP1_HWIP,
1315 UVD_HWIP,
1316 VCN_HWIP = UVD_HWIP,
1317 VCE_HWIP,
1318 DF_HWIP,
1319 DCE_HWIP,
1320 OSSSYS_HWIP,
1321 SMUIO_HWIP,
1322 PWR_HWIP,
1323 NBIF_HWIP,
1324 THM_HWIP,
1325 CLK_HWIP,
1326 MAX_HWIP
1327 };
1328
1329 #define HWIP_MAX_INSTANCE 6
1330
1331 struct amd_powerplay {
1332 void *pp_handle;
1333 const struct amd_pm_funcs *pp_funcs;
1334 uint32_t pp_feature;
1335 };
1336
1337 #define AMDGPU_RESET_MAGIC_NUM 64
1338 struct amdgpu_device {
1339 struct device *dev;
1340 struct drm_device *ddev;
1341 struct pci_dev *pdev;
1342
1343 #ifdef CONFIG_DRM_AMD_ACP
1344 struct amdgpu_acp acp;
1345 #endif
1346
1347 /* ASIC */
1348 enum amd_asic_type asic_type;
1349 uint32_t family;
1350 uint32_t rev_id;
1351 uint32_t external_rev_id;
1352 unsigned long flags;
1353 int usec_timeout;
1354 const struct amdgpu_asic_funcs *asic_funcs;
1355 bool shutdown;
1356 bool need_dma32;
1357 bool need_swiotlb;
1358 bool accel_working;
1359 struct work_struct reset_work;
1360 struct notifier_block acpi_nb;
1361 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1362 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1363 unsigned debugfs_count;
1364 #if defined(CONFIG_DEBUG_FS)
1365 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1366 #endif
1367 struct amdgpu_atif *atif;
1368 struct amdgpu_atcs atcs;
1369 struct mutex srbm_mutex;
1370 /* GRBM index mutex. Protects concurrent access to GRBM index */
1371 struct mutex grbm_idx_mutex;
1372 struct dev_pm_domain vga_pm_domain;
1373 bool have_disp_power_ref;
1374
1375 /* BIOS */
1376 bool is_atom_fw;
1377 uint8_t *bios;
1378 uint32_t bios_size;
1379 struct amdgpu_bo *stolen_vga_memory;
1380 uint32_t bios_scratch_reg_offset;
1381 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1382
1383 /* Register/doorbell mmio */
1384 resource_size_t rmmio_base;
1385 resource_size_t rmmio_size;
1386 void __iomem *rmmio;
1387 /* protects concurrent MM_INDEX/DATA based register access */
1388 spinlock_t mmio_idx_lock;
1389 /* protects concurrent SMC based register access */
1390 spinlock_t smc_idx_lock;
1391 amdgpu_rreg_t smc_rreg;
1392 amdgpu_wreg_t smc_wreg;
1393 /* protects concurrent PCIE register access */
1394 spinlock_t pcie_idx_lock;
1395 amdgpu_rreg_t pcie_rreg;
1396 amdgpu_wreg_t pcie_wreg;
1397 amdgpu_rreg_t pciep_rreg;
1398 amdgpu_wreg_t pciep_wreg;
1399 /* protects concurrent UVD register access */
1400 spinlock_t uvd_ctx_idx_lock;
1401 amdgpu_rreg_t uvd_ctx_rreg;
1402 amdgpu_wreg_t uvd_ctx_wreg;
1403 /* protects concurrent DIDT register access */
1404 spinlock_t didt_idx_lock;
1405 amdgpu_rreg_t didt_rreg;
1406 amdgpu_wreg_t didt_wreg;
1407 /* protects concurrent gc_cac register access */
1408 spinlock_t gc_cac_idx_lock;
1409 amdgpu_rreg_t gc_cac_rreg;
1410 amdgpu_wreg_t gc_cac_wreg;
1411 /* protects concurrent se_cac register access */
1412 spinlock_t se_cac_idx_lock;
1413 amdgpu_rreg_t se_cac_rreg;
1414 amdgpu_wreg_t se_cac_wreg;
1415 /* protects concurrent ENDPOINT (audio) register access */
1416 spinlock_t audio_endpt_idx_lock;
1417 amdgpu_block_rreg_t audio_endpt_rreg;
1418 amdgpu_block_wreg_t audio_endpt_wreg;
1419 void __iomem *rio_mem;
1420 resource_size_t rio_mem_size;
1421 struct amdgpu_doorbell doorbell;
1422
1423 /* clock/pll info */
1424 struct amdgpu_clock clock;
1425
1426 /* MC */
1427 struct amdgpu_gmc gmc;
1428 struct amdgpu_gart gart;
1429 dma_addr_t dummy_page_addr;
1430 struct amdgpu_vm_manager vm_manager;
1431 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1432
1433 /* memory management */
1434 struct amdgpu_mman mman;
1435 struct amdgpu_vram_scratch vram_scratch;
1436 struct amdgpu_wb wb;
1437 atomic64_t num_bytes_moved;
1438 atomic64_t num_evictions;
1439 atomic64_t num_vram_cpu_page_faults;
1440 atomic_t gpu_reset_counter;
1441 atomic_t vram_lost_counter;
1442
1443 /* data for buffer migration throttling */
1444 struct {
1445 spinlock_t lock;
1446 s64 last_update_us;
1447 s64 accum_us; /* accumulated microseconds */
1448 s64 accum_us_vis; /* for visible VRAM */
1449 u32 log2_max_MBps;
1450 } mm_stats;
1451
1452 /* display */
1453 bool enable_virtual_display;
1454 struct amdgpu_mode_info mode_info;
1455 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
1456 struct work_struct hotplug_work;
1457 struct amdgpu_irq_src crtc_irq;
1458 struct amdgpu_irq_src pageflip_irq;
1459 struct amdgpu_irq_src hpd_irq;
1460
1461 /* rings */
1462 u64 fence_context;
1463 unsigned num_rings;
1464 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1465 bool ib_pool_ready;
1466 struct amdgpu_sa_manager ring_tmp_bo;
1467
1468 /* interrupts */
1469 struct amdgpu_irq irq;
1470
1471 /* powerplay */
1472 struct amd_powerplay powerplay;
1473 bool pp_force_state_enabled;
1474
1475 /* dpm */
1476 struct amdgpu_pm pm;
1477 u32 cg_flags;
1478 u32 pg_flags;
1479
1480 /* amdgpu smumgr */
1481 struct amdgpu_smumgr smu;
1482
1483 /* gfx */
1484 struct amdgpu_gfx gfx;
1485
1486 /* sdma */
1487 struct amdgpu_sdma sdma;
1488
1489 /* uvd */
1490 struct amdgpu_uvd uvd;
1491
1492 /* vce */
1493 struct amdgpu_vce vce;
1494
1495 /* vcn */
1496 struct amdgpu_vcn vcn;
1497
1498 /* firmwares */
1499 struct amdgpu_firmware firmware;
1500
1501 /* PSP */
1502 struct psp_context psp;
1503
1504 /* GDS */
1505 struct amdgpu_gds gds;
1506
1507 /* display related functionality */
1508 struct amdgpu_display_manager dm;
1509
1510 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1511 int num_ip_blocks;
1512 struct mutex mn_lock;
1513 DECLARE_HASHTABLE(mn_hash, 7);
1514
1515 /* tracking pinned memory */
1516 atomic64_t vram_pin_size;
1517 atomic64_t visible_pin_size;
1518 atomic64_t gart_pin_size;
1519
1520 /* amdkfd interface */
1521 struct kfd_dev *kfd;
1522
1523 /* soc15 register offset based on ip, instance and segment */
1524 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1525
1526 const struct amdgpu_nbio_funcs *nbio_funcs;
1527 const struct amdgpu_df_funcs *df_funcs;
1528
1529 /* delayed work_func for deferring clockgating during resume */
1530 struct delayed_work late_init_work;
1531
1532 struct amdgpu_virt virt;
1533 /* firmware VRAM reservation */
1534 struct amdgpu_fw_vram_usage fw_vram_usage;
1535
1536 /* link all shadow bo */
1537 struct list_head shadow_list;
1538 struct mutex shadow_list_lock;
1539 /* keep an lru list of rings by HW IP */
1540 struct list_head ring_lru_list;
1541 spinlock_t ring_lru_list_lock;
1542
1543 /* record hw reset is performed */
1544 bool has_hw_reset;
1545 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1546
1547 /* record last mm index being written through WREG32*/
1548 unsigned long last_mm_index;
1549 bool in_gpu_reset;
1550 struct mutex lock_reset;
1551 };
1552
amdgpu_ttm_adev(struct ttm_bo_device * bdev)1553 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1554 {
1555 return container_of(bdev, struct amdgpu_device, mman.bdev);
1556 }
1557
1558 int amdgpu_device_init(struct amdgpu_device *adev,
1559 struct drm_device *ddev,
1560 struct pci_dev *pdev,
1561 uint32_t flags);
1562 void amdgpu_device_fini(struct amdgpu_device *adev);
1563 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1564
1565 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1566 uint32_t acc_flags);
1567 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1568 uint32_t acc_flags);
1569 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1570 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1571
1572 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1573 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1574
1575 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1576 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1577 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1578 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
1579
1580 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1581 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1582
1583 int emu_soc_asic_init(struct amdgpu_device *adev);
1584
1585 /*
1586 * Registers read & write functions.
1587 */
1588
1589 #define AMDGPU_REGS_IDX (1<<0)
1590 #define AMDGPU_REGS_NO_KIQ (1<<1)
1591
1592 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1593 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1594
1595 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1596 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1597
1598 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1599 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1600 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1601 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1602 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1603 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1604 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1605 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1606 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1607 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1608 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1609 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1610 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1611 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1612 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1613 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1614 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1615 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1616 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1617 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1618 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1619 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1620 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1621 #define WREG32_P(reg, val, mask) \
1622 do { \
1623 uint32_t tmp_ = RREG32(reg); \
1624 tmp_ &= (mask); \
1625 tmp_ |= ((val) & ~(mask)); \
1626 WREG32(reg, tmp_); \
1627 } while (0)
1628 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1629 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1630 #define WREG32_PLL_P(reg, val, mask) \
1631 do { \
1632 uint32_t tmp_ = RREG32_PLL(reg); \
1633 tmp_ &= (mask); \
1634 tmp_ |= ((val) & ~(mask)); \
1635 WREG32_PLL(reg, tmp_); \
1636 } while (0)
1637 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1638 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1639 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1640
1641 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1642 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1643 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1644 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1645
1646 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1647 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1648
1649 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1650 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1651 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1652
1653 #define REG_GET_FIELD(value, reg, field) \
1654 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1655
1656 #define WREG32_FIELD(reg, field, val) \
1657 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1658
1659 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1660 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1661
1662 /*
1663 * BIOS helpers.
1664 */
1665 #define RBIOS8(i) (adev->bios[i])
1666 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1667 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1668
1669 static inline struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring * ring)1670 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1671 {
1672 struct amdgpu_device *adev = ring->adev;
1673 int i;
1674
1675 for (i = 0; i < adev->sdma.num_instances; i++)
1676 if (&adev->sdma.instance[i].ring == ring)
1677 break;
1678
1679 if (i < AMDGPU_MAX_SDMA_INSTANCES)
1680 return &adev->sdma.instance[i];
1681 else
1682 return NULL;
1683 }
1684
1685 /*
1686 * ASICs macro.
1687 */
1688 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1689 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1690 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1691 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1692 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1693 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1694 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1695 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1696 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1697 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1698 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1699 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1700 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1701 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1702 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1703 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
1704 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
1705 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
1706 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1707 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
1708 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
1709 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1710 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1711 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1712 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1713 #define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
1714 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1715 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1716 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1717 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1718 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1719 #define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
1720 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1721 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1722 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
1723 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1724 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
1725 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1726 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1727 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1728 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1729 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
1730 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
1731 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
1732 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1733 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1734 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
1735 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1736 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
1737 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1738 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1739 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1740 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1741 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1742 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1743 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1744 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1745 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1746 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
1747 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1748 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1749 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1750 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
1751 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1752 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
1753 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
1754 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1755 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1756 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
1757
1758 /* Common functions */
1759 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1760 struct amdgpu_job* job, bool force);
1761 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1762 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1763 void amdgpu_display_update_priority(struct amdgpu_device *adev);
1764
1765 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1766 u64 num_vis_bytes);
1767 void amdgpu_device_vram_location(struct amdgpu_device *adev,
1768 struct amdgpu_gmc *mc, u64 base);
1769 void amdgpu_device_gart_location(struct amdgpu_device *adev,
1770 struct amdgpu_gmc *mc);
1771 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1772 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1773 const u32 *registers,
1774 const u32 array_size);
1775
1776 bool amdgpu_device_is_px(struct drm_device *dev);
1777 /* atpx handler */
1778 #if defined(CONFIG_VGA_SWITCHEROO)
1779 void amdgpu_register_atpx_handler(void);
1780 void amdgpu_unregister_atpx_handler(void);
1781 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1782 bool amdgpu_is_atpx_hybrid(void);
1783 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1784 bool amdgpu_has_atpx(void);
1785 #else
amdgpu_register_atpx_handler(void)1786 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1787 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1788 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1789 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1790 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1791 static inline bool amdgpu_has_atpx(void) { return false; }
1792 #endif
1793
1794 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1795 void *amdgpu_atpx_get_dhandle(void);
1796 #else
amdgpu_atpx_get_dhandle(void)1797 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1798 #endif
1799
1800 /*
1801 * KMS
1802 */
1803 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1804 extern const int amdgpu_max_kms_ioctl;
1805
1806 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1807 void amdgpu_driver_unload_kms(struct drm_device *dev);
1808 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1809 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1810 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1811 struct drm_file *file_priv);
1812 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1813 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1814 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1815 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1816 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1817 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1818 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1819 unsigned long arg);
1820
1821 /*
1822 * functions used by amdgpu_encoder.c
1823 */
1824 struct amdgpu_afmt_acr {
1825 u32 clock;
1826
1827 int n_32khz;
1828 int cts_32khz;
1829
1830 int n_44_1khz;
1831 int cts_44_1khz;
1832
1833 int n_48khz;
1834 int cts_48khz;
1835
1836 };
1837
1838 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1839
1840 /* amdgpu_acpi.c */
1841 #if defined(CONFIG_ACPI)
1842 int amdgpu_acpi_init(struct amdgpu_device *adev);
1843 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1844 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1845 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1846 u8 perf_req, bool advertise);
1847 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1848 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1849 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_fini(struct amdgpu_device * adev)1850 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1851 #endif
1852
1853 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1854 uint64_t addr, struct amdgpu_bo **bo,
1855 struct amdgpu_bo_va_mapping **mapping);
1856
1857 #if defined(CONFIG_DRM_AMD_DC)
1858 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1859 #else
amdgpu_dm_display_resume(struct amdgpu_device * adev)1860 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1861 #endif
1862
1863 #include "amdgpu_object.h"
1864 #endif
1865
